Lead Load-Store Verification Architect

Socket.dev; Town of Fishkill (NY); On-site; USD 120,000 - 160,000; Full time

Job summary

AMD is seeking an outstanding candidate to provide technical leadership for load/store verification execution for next-gen processors. You will maintain and enhance verification methodologies, build infrastructure, and collaborate with RTL/Design teams to meet goals.

The ideal candidate will have strong communication skills and the ability to work with a diverse team, with hands-on experience in Verilog/SystemVerilog, Perl, and C/C++.

Qualifications

• BS or MS in CS or EE with significant industry relevance.
• Proven expertise in load/store verification for CPU designs.
• Strong leadership experience in verification teams and projects.
• Experience with functional verification of microprocessor designs.
• Proficiency in Verilog/SystemVerilog HDL, Perl, C/C++, and scripting.
• Knowledge of logic simulation and Verilog simulators is a plus.
• Good understanding of computer architecture and assembly language.
• Hands-on debugging of high-speed processor tests and regression suites.

Responsibilities

• Perform functional verification of high-speed CPUs across SoC, core, and block hierarchies.
• Develop infrastructure, test plans, and debug capabilities for full-chip and block-level verification.
• Create automated regression using x86 assembly tests and directed exercises.
• Resolve simulation discrepancies and analyze coverage to close gaps.
• Support next-gen LSDC rewrite and related verification efforts.

Skills

CPU Architecture

Load/Store verification

Technical leadership

Functional verification

Verilog/SystemVerilog

Perl/C/C++ programming

Logic simulation

Verilog simulators

Assembly programming

Computer architecture

Education

BS or MS in CS or EE

Tools

Verilog

SystemVerilog

HDL

Perl

C/C++

Job description

AMD is seeking an outstanding candidate to provide technical leadership for load/store verification execution for next-gen processors. You will maintain and enhance verification methodologies, build infrastructure, and collaborate with RTL/Design teams to meet goals.

The ideal candidate will have strong communication skills and the ability to work with a diverse team, with hands-on experience in Verilog/SystemVerilog, Perl, and C/C++.