Lead High-Speed PCB Layout Engineer (Equity Eligible)

Array Labs

Redwood City, Northern (CA, KY)

Hybrid

USD 160,000 - 200,000

Full time

14 days+
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Job summary

Array Labs hires a Lead High-Speed PCB Layout Engineer to own the physical implementation of high-speed digital and mixed-signal electronics in Altium. You will translate schematics and performance requirements into layouts and functional designs, including stack-up, constraints, and return-path strategy.

You will partner with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases, impacting signal integrity, power integrity,

Qualifications

  • Bachelor’s degree in electrical engineering or related field.
  • 8+ years of experience in high-speed PCB layout and release.
  • Strong teamwork and communication skills.
  • Ability to work in a fast-paced environment with tight timelines.
  • Proven self-motivation and personal accountability.

Responsibilities

  • Own high-speed PCB layout from placement to manufacturing release in Altium.
  • Define stack-ups, impedance targets, matching constraints, and return-path strategies.
  • Translate schematics into layouts meeting SI/PI requirements across domains.
  • Collaborate with design, firmware, mechanical, and test teams on constraints and reviews.
  • Drive DFM/DFT considerations and release artifacts with fabrication partners.

Skills

Teamwork
Communication
Self-motivation
Accountability
Time management

Education

B.S. in Electrical Engineering

Tools

Altium Designer
Allegro
OrCAD
Ansys SIwave
Keysight Power Analyzer
HyperLynx
Sigrity

Job description

Array Labs hires a Lead High-Speed PCB Layout Engineer to own the physical implementation of high-speed digital and mixed-signal electronics in Altium. You will translate schematics and performance requirements into layouts and functional designs, including stack-up, constraints, and return-path strategy.

You will partner with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases, impacting signal integrity, power integrity,

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