Lead Design Verification Engineer - High-Speed Silicon

Cisco; Allentown (Lehigh County); On-site; USD 192,000 - 276,000; Full time

Job summary

Cisco is seeking a Design Verification Technical Leader to drive verification for high-speed silicon photonics driver ICs used across routing, switching, and data center platforms. You will lead verification strategy, coordinate across sites, and mentor engineers to ensure robust testability and performance.

Lead efforts for block- and chip-level verification, influence architecture, and collaborate with architecture and design teams to deliver scalable verification environments.

Qualifications

• Experience in SystemVerilog, UVM, and verification methodologies.
• Experience owning and delivering verification for large-scale SoCs or subsystems.
• Experience leading verification teams or projects.
• Experience scripting and automation (Python, Perl, TCL, or Shell).

Responsibilities

• Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites.
• Lead verification at block & chip level with high-speed IPs (ODSP, D2D IP, SerDes XSR/PAM4, Integrated drivers/TIA).
• Review specifications, participate in design reviews, influence architecture for testability and verification efficiency.
• Mentor and coach verification engineers, driving continuous improvement in technical skills and execution.
• Debug complex silicon and system-level issues during bring-up phases.
• Support post-silicon bring-up and optimize integration and performance.

Skills

SystemVerilog

UVM

Python

Education

Bachelor’s degree in Electrical or Computer engineering

Master’s degree in Electrical or Computer Engineering

PhD in Electrical/Computer Engineering

Tools

Veloce

HAPS

Job description

Cisco is seeking a Design Verification Technical Leader to drive verification for high-speed silicon photonics driver ICs used across routing, switching, and data center platforms. You will lead verification strategy, coordinate across sites, and mentor engineers to ensure robust testability and performance.

Lead efforts for block- and chip-level verification, influence architecture, and collaborate with architecture and design teams to deliver scalable verification environments.