Lead CPU RTL Design Engineer

Google; Mountain View (CA); On-site; USD 183,000 - 271,000; Full time

Job summary

Join a leading team at Google focused on developing custom silicon solutions. This role involves shaping the next generation of hardware with an emphasis on performance and efficiency, requiring extensive experience in CPU or AI accelerator design. The position offers a competitive salary and benefits package.

Benefits

Bonus

Equity

Comprehensive benefits package

Qualifications

• At least 8 years of experience in CPU or AI accelerator logic/RTL design.
• Proficiency with System Verilog and related design processes.
• Experience leading front-end design for modern processor components.

Responsibilities

• Develop CPU subsystems focusing on advanced branch prediction algorithms.
• Propose microarchitecture features to enhance performance.
• Coordinate with teams to meet quality, frequency, power, and area targets.

Skills

RTL languages

Microarchitecture definition

PPA optimizations

SoC design

ARM Instruction Set Architecture

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in relevant field

Job description

Minimum qualifications:

1. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
2. At least 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
3. Proficiency with RTL languages (System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

1. Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture, or a related field.
2. Experience leading front-end design for modern processor components or AI accelerators.
3. Experience with ARM Instruction Set Architecture.
4. Experience with SoC design, architecture, and integration.

Job Description:

Join a team at Google that develops custom silicon solutions powering innovative products loved worldwide. Contribute to shaping the next generation of hardware, focusing on performance, efficiency, and integration.

Location and Compensation:

The US base salary range for this full-time role is $183,000-$271,000, plus bonus, equity, and benefits. Salary ranges are role-, level-, and location-dependent. Specific details will be provided during the hiring process.

Note: Listed compensation reflects the base salary only; bonus, equity, and benefits are additional. Learn more about benefits at Google Benefits.

Responsibilities:

• Participate in developing CPU subsystems, focusing on advanced branch prediction algorithms and Instruction Fetch Unit (IFU).
• Propose microarchitecture features to enhance performance, collaborating with Software, Architecture, and Performance teams for trade-off analyses.
• Communicate the advantages and disadvantages of microarchitecture enhancements, ensuring designs meet Performance, Power, and Area (PPA) goals with production quality.
• Coordinate with Verification, Physical Design, and Power teams to meet quality, frequency, power, and area targets.
• Familiarize with modern design techniques and interpret them into design constructs and languages to guide performance evaluation.

Google is an equal opportunity employer, committed to diversity and inclusion. We consider all qualified applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status. For accommodations, please complete our Accommodations form.