Sr. /Staff/Principal Analog Mixed-Signal Design Engineer

OMNIVISION; Santa Clara (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

A leading semiconductor company is seeking a Sr. /Staff/Principal Analog Mixed-Signal Design Engineer for its Santa Clara office. The role entails designing and developing advanced IP, particularly for Multi-Gbps applications. Candidates should have strong experience in analog/mixed-signal design with a solid educational background. Join a team at the forefront of technology development, where your contributions directly impact cutting-edge products.

Qualifications

• Design and develop Multi-Gbps PAM4 SerDes IP.
• Familiar with Cadence analog flow and simulations.
• 3+ years of experience in the field.

Responsibilities

• Design, simulation, and verification of high-speed analog signaling.
• Interface verifications between analog and digital.
• Support layout optimizations for high-speed applications.

Skills

Analog/Mixed-Signal design

Design and debug experience

High speed test

Layout design

Education

Masters of Electrical Engineering

PhD

Tools

Cadence analog design/layout

Spice/SpectreMDL simulations

Job description

Sr. /Staff/Principal Analog Mixed-Signal Design Engineer

Join to apply for the Sr. /Staff/Principal Analog Mixed-Signal Design Engineer role at OMNIVISION

Sr. /Staff/Principal Analog Mixed-Signal Design Engineer

Join to apply for the Sr. /Staff/Principal Analog Mixed-Signal Design Engineer role at OMNIVISION

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Overview :

Responsible for design, development, and refinement of Multi-Gbps PAM4 SerDes IP. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock designs is a significant plus.

Description

Overview :

Responsible for design, development, and refinement of Multi-Gbps PAM4 SerDes IP. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock designs is a significant plus.

Need to work closely with system and test engineers to develop high speed interface, package/board, and system clocks in image sensor and bridge chip products.

Responsibilities

• Analog/Mixed-Signal design, simulation and verifications esp PAM4 receiver designs such as TI-SAR ADC, CTLE/DFE and other blocks in AFE.
• CDR design experience is significant plus.
• High speed test with scope and BERT.
• Layout design and support. Need to get involved into layout optimizations for high speed or high precision performance directly.
• Interface verifications between analog and digital.
• IP and design spec documentations.
  
  

Requirements

• Familiar with Cadence analog design/layout flow and spice/spectreMDL simulations.
• Masters of Electrical Engineering or PhD with 3+ yrs of expertise.
  
  

Annual base salary for this role in California, US is expected to be between $150,000 - $250,000. Actual pay will be determined on a number of factors such as relevant skills, education, experience, and the pay of employees in the similar role.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

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