Layout Designer

WorkGenius Group; Cupertino (CA); On-site; USD 80,000 - 100,000; Full time

Job summary

An innovative technology firm is seeking a skilled Layout Engineer to design intricate layouts for analog and mixed-signal circuits. The role demands expertise in interpreting schematics, optimizing floorplans, and performing physical verification checks. You will work closely with circuit designers to ensure design intent is met while utilizing industry-standard EDA tools in advanced nodes. This position offers a chance to contribute significantly to cutting-edge projects in a collaborative environment, making it ideal for professionals eager to advance their careers in the semiconductor industry.

Qualifications

• 5+ years in analog/mixed-signal layout design in deep sub-micron CMOS.
• Experience in FinFET nodes (7nm, 5nm, 3nm) is required.

Responsibilities

• Interpret schematics and optimize floorplans for performance and manufacturability.
• Perform physical verification checks and collaborate with circuit designers.

Skills

Analog/Mixed-Signal Layout Design

Physical Verification (LVS/DRC/ERC)

EDA Tools (Cadence Virtuoso, Mentor Calibre)

Scripting (SKILL, Python, Perl)

Communication Skills

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Microelectronics

Tools

Cadence Virtuoso

Mentor Calibre

Synopsys Custom Compiler

Innovus (Digital APR Tools)

Job description

Job Title: Layout Engineer / Layout Designer (Analog and Mixed Signal)

Join our team to design and deliver complex layouts for analog and mixed-signal circuits, including PLLs, ADCs, DACs, LDOs, amplifiers, and high-speed interfaces.

Responsibilities:

• Interpret schematics and floorplans to meet performance, area, and power targets.
• Analyze and optimize floorplans for performance, routability, and manufacturability.
• Perform physical verification checks (DRC, LVS, ERC) and ensure fast closure.
• Collaborate with circuit designers to understand critical design intent, negotiate trade-offs, and meet milestones.
• Use industry-standard EDA tools and methodologies in advanced nodes (7nm, 5nm, and beyond).
• Maintain thorough documentation, version control, and enable layout reuse.
• Identify and resolve physical design bottlenecks proactively.
• Apply advanced knowledge of parasitic effects, matching, symmetry, shielding, and routing best practices.

Requirements:

• Minimum 5 years of hands-on experience in analog/mixed-signal layout design in deep sub-micron CMOS processes.
• At least 2 years of experience in FinFET nodes (7nm, 5nm, 3nm).
• Strong expertise in EDA tools like Cadence Virtuoso, Mentor Calibre, Synopsys Custom Compiler; familiarity with digital APR tools like Innovus is a plus.
• Solid understanding of physical verification (LVS/DRC/ERC), parasitic extraction, and reliability analysis.
• Familiarity with scripting languages (SKILL, Python, Perl) for automation.
• Excellent communication and collaboration skills across disciplines.
• Experience with RF, high-speed I/O, or power management layout is a plus.
• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.

Additional Information:

• Hourly rate is commensurate with experience and is an estimated range provided by WorkGenius.

Seniority level: Mid-Senior level

Employment type: Contract

Job function: Design

Industries: Technology, Information and Media