Layout Designer

Russell Tobin; Cupertino (CA); On-site; USD 80,000 - 100,000; Full time

Job summary

Join a leading consumer electronics organization as a Mask Layout Designer III, where you will be at the forefront of designing innovative mask layouts for analog circuits. This role involves close collaboration with circuit designers and layout leads to ensure precise integration into System-on-a-chip (SoC) technology. With a focus on quality and efficiency, you will assess and execute layout tasks while adhering to deadlines. This is an exciting opportunity to contribute to cutting-edge projects in a dynamic engineering environment, where your expertise will help shape the future of consumer electronics.

Qualifications

• 6+ years of experience in layout design for analog circuits.
• Expertise in designing layouts for SubMicron CMOS circuits.

Responsibilities

• Design mask layouts for analog circuits for SoC integration.
• Collaborate with circuit designers to meet layout requirements.

Skills

Layout design of analog blocks

Using CALIBRE DRC, ERC, LVS tools

Understanding IR drop, RC delay

Applying analog and DFM best practices

Education

Bachelor’s degree

Master’s degree

Tools

CALIBRE

Job description

Job Title: Mask Layout Designer III

The Engineering Team at Russell Tobin & Associates is hiring a Mask Layout Engineer at a leading consumer electronics organization near San Jose, CA.

Position Details

• Employment Type: 11 Months Contract with potential extension
• Pay Rate: $50/hr - $70/hr on W2
• Location: Onsite in San Jose, CA

Responsibilities

• Design mask layouts for analog circuits for integration into System-on-a-chip (SoC)
• Collaborate with circuit designers and layout leads to understand requirements
• Assess, plan, and execute layout tasks
• Meet deadlines and communicate potential issues

Requirements

• Bachelor’s degree with 6+ years or Master’s degree with 3+ years of relevant experience
• 3+ years experience in:
• Layout design of analog blocks, resistors, capacitors, ESD structures with tight matching, low noise, low power
• IR drop, RC delay, electromigration, self-heating, cross capacitance
• Using CALIBRE DRC, ERC, LVS tools
• Designing analog/mixed-signal layouts for SubMicron CMOS circuits
• Applying analog and DFM best practices

Must be authorized to work in the United States.