Latency-Driven Design Verification Engineer

Engtal; United States; Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Engtal is seeking a Design Verification Engineer to join its hardware R&D team in the United States. This role focuses on verification of high-performance digital hardware where nanoseconds matter and latency must be minimized.

You will collaborate with RTL, FPGA and software engineers, building robust verification environments, deriving/testbenches, and driving regression frameworks to ensure reliable, low-latency hardware solutions.

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering or a related technical discipline.
• 3+ years of hardware design verification experience.
• Strong hands-on experience with UVM.
• Strong knowledge of SystemVerilog / Verilog.
• Experience developing both system-level and block-level testbenches.
• Experience using industry-standard third-party EDA tools.

Responsabilidades

• Develop and execute verification strategies for complex digital hardware designs.
• Build system-level and block-level UVM testbenches.
• Collaborate closely with RTL and software engineers to validate complex systems.
• Develop automated verification environments that enable rapid development and fast turnaround.
• Create and maintain regression testing and automation frameworks.
• Debug complex RTL and verification issues.
• Work with industry-standard EDA simulation and verification tools.
• Develop scripts and tooling to improve verification efficiency.
• Contribute to verification methodology and processes across the wider hardware team.

Conocimientos

UVM

SystemVerilog

Verilog

Testbenches

Scripting

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering

Herramientas

EDA tools

Descripción del empleo

Engtal is seeking a Design Verification Engineer to join its hardware R&D team in the United States. This role focuses on verification of high-performance digital hardware where nanoseconds matter and latency must be minimized.

You will collaborate with RTL, FPGA and software engineers, building robust verification environments, deriving/testbenches, and driving regression frameworks to ensure reliable, low-latency hardware solutions.