Kernel Engineer — Custom AI Silicon, High-Perf Compute

River AI; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, and vision benefits

Unlimited PTO

Relocation support

Competitive equity

Visa sponsorship

Job summary

River AI seeks exceptional kernel engineers to build the foundational compute engine for its greenfield silicon. You will design and implement robust code-generation frameworks that emit optimized ISA assembly for our custom hardware architecture.

You’ll optimize core primitives (GEMMs, attention, convolutions) and tune microarchitectural aspects like scheduling, registers, and memory movement, collaborating across compiler, silicon, and research teams to maximize performance.

Qualifications

• Bachelor's degree and 5+ years in low-level performance programming.
• Deep understanding of hardware programming models and optimized kernels.
• Proficiency in modern C++ for code generation frameworks.

Responsibilities

• Design and build C++ code-generation frameworks to emit optimized ISA assembly.
• Author and optimize deep learning primitives for custom silicon.
• Automate instruction scheduling, register allocation, and software-pipelining.
• Develop memory hierarchy strategies to maximize on-chip SRAM utilization.
• Collaborate with RTL/architecture teams to influence future compute units.
• Benchmark generated code against hardware simulators and ensure correctness.

Skills

Low-level performance programming

Hardware programming models (CUDA/Trit

Modern C++ meta-programming

Kernel/assembly code generation

Education

Bachelor’s degree in Computer Engineering, Computer Science, or Electrical Engineering

Tools

CUDA

Triton

CUTLASS

Custom accelerator ISA

Job description

River AI seeks exceptional kernel engineers to build the foundational compute engine for its greenfield silicon. You will design and implement robust code-generation frameworks that emit optimized ISA assembly for our custom hardware architecture.

You’ll optimize core primitives (GEMMs, attention, convolutions) and tune microarchitectural aspects like scheduling, registers, and memory movement, collaborating across compiler, silicon, and research teams to maximize performance.