Junior ASIC Design Engineer - Verilog & Debug

Cisco; San Jose (CA); On-site; USD 45,000 - 75,000; Part time

Job summary

Cisco's Silicon One team is seeking an ASIC Design Engineer intern to help design and integrate next-generation silicon for core networking products. You will work with cross-functional teams across design, verification, and physical design to ensure high-performance, power-efficient solutions.

You will gain hands-on experience in Verilog/SystemVerilog, RTL implementation, timing analysis, and full-chip bring-up, while contributing to post-silicon validation and debugging efforts.

Qualifications

• Currently enrolled in an undergraduate degree program (Associate's or Bachelor's).
• Qualifying education should be in ASIC Design, Engineering or a related field.
• Expected to continue enrollment in degree program following completion of the internship.
• Foundational knowledge and academic project experience in Verilog/SystemVerilog.
• Demonstrated ability to perform interactive and wave-form based debugging on digital systems.

Responsibilities

• Participate in the creation of design specifications and in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing, performance, and power requirements.
• Contribute to full chip integration and support timing methodology and analysis.
• Develop, analyze, and ensure functional coverage.
• Collaborate with the verification team to address design bugs and close code coverage.
• Collaborate with the physical design team to resolve timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Perform diagnostic and post-silicon validation tests in the lab.

Skills

Verilog

SystemVerilog

Debugging

Python

Networking knowledge

Communication

Education

Undergraduate degree (Associate or Bachelor's)

ASIC Design, Engineering or related field

Expected to continue enrollment

Tools

Scripting

Job description

Cisco's Silicon One team is seeking an ASIC Design Engineer intern to help design and integrate next-generation silicon for core networking products. You will work with cross-functional teams across design, verification, and physical design to ensure high-performance, power-efficient solutions.

You will gain hands-on experience in Verilog/SystemVerilog, RTL implementation, timing analysis, and full-chip bring-up, while contributing to post-silicon validation and debugging efforts.