Intern: Physical Design & DFT for Next‑Gen AI Chip

Tenstorrent; Santa Clara (CA); On-site; USD 69,000 - 96,000; Full time

Job summary

Tenstorrent is seeking interns for RTL-centric work and physical design objectives. You will contribute to synthesis, floorplanning, place & route, and timing closure, while exploring ML-assisted physical design and DFT concepts such as JTAG, ATPG, and MBIST.

The position offers exposure to a commercial PnR toolchain, hands-on learning of timing/power/area tradeoffs, and teamwork across hardware and software domains. On-site opportunities in multiple U.S. locations.

Qualifications

• Pursuing a BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, or Software Engineering.

Responsibilities

• Physical Design: Synthesis, floorplanning, place & route, clocking, timing closure.
• Advanced Physical Design: ML-assisted design flows.
• DFT: JTAG, Scan/ATP, MBIST.
• Gain hands-on experience in Design-for-Testability (DFT) to enable efficient testing.

Education

BS, MS, or PhD in Electrical or Computer Engineering, Computer Science, Software Engineering

Tools

Synopsys

Cadence

Job description

Tenstorrent is seeking interns for RTL-centric work and physical design objectives. You will contribute to synthesis, floorplanning, place & route, and timing closure, while exploring ML-assisted physical design and DFT concepts such as JTAG, ATPG, and MBIST.

The position offers exposure to a commercial PnR toolchain, hands-on learning of timing/power/area tradeoffs, and teamwork across hardware and software domains. On-site opportunities in multiple U.S. locations.