IC Layout Engineer

MediaTek; Irvine (CA); On-site; USD 85,900 - 137,500; Full time

Benefits offered by this job

Comprehensive health insurance

401K plan

Paid time off (PTO)

Job summary

MediaTek in Irvine, California, seeks a skilled engineer to design high-quality layouts for various semiconductor products. Candidates should be proficient in Virtuoso and Calibre tools, with experience in high-speed circuits and knowledge of N7/N5/N3 processes. The role offers a salary range of $85,900 - $137,500 plus potential performance bonuses. Comprehensive health benefits and a 401K plan are included.

Qualifications

• Proficient in Virtuoso and Calibre tools.
• Familiar with validating LVS/DRC/ERC/ANT/ESD/LPE.
• Experience with high-speed circuits, hybrid circuits, low-dropout regulators, phase-locked loops, and basic ESD knowledge.
• Knowledge of N7/N5/N3 processes.

Responsibilities

• Work closely with the design team to develop high-quality layouts.
• Perform layout in CMOS or FinFET technologies.
• Design layout, verification, and parasitic extraction.

Skills

Proficient in Virtuoso and Calibre tools

Validating LVS/DRC/ERC/ANT/ESD/LPE

Experience with high-speed circuits

Tools

Cadence design environment

Job description

MediaTek Incorporated is a global fabless semiconductor company that enables nearly 2 billion connected devices a year. We are a market leader in developing innovative systems‑on‑chip (SoC) for mobile devices, automotive, home entertainment, connectivity and IoT products. Our dedication to innovation has positioned us as a driving market force in highly power‑efficient mobile technologies, automotive solutions, and advanced multimedia products such as smartphones, tablets, digital televisions, 5G, Voice Assistant Devices, and wearables.

Responsibilities

• Work closely with the design team to develop high‑quality layouts for products, data converters, power management circuitry, and various other IP.
• Perform layout in CMOS or FinFET technologies for high‑speed front ends, ADCs, DACs, PLLs, and other mixed‑signal IP.
• Design layout, verification, and parasitic extraction, all using the Cadence design environment.

Qualifications

• Proficient in Virtuoso and Calibre tools.
• Familiar with validating LVS/DRC/ERC/ANT/ESD/LPE.
• Experience with high‑speed circuits, hybrid circuits, low‑dropout regulators, phase‑locked loops, and basic ESD knowledge.
• Knowledge of N7/N5/N3 processes.

Salary range: $85,900 -$137,500. Employee may be eligible for performance bonus, short‑ and long‑term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience, and qualifications.

Benefits include comprehensive health insurance coverage, life and disability insurance, savings plan, company‑paid holidays, paid time off (PTO), parental leave, and a 401K plan.

MediaTek is an Equal Opportunity Employer committed to inclusion and diversity for all, regardless of age, ancestry, color, disability, family care, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (including pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.