Hybrid Analog IC Layout Engineer — Cadence Virtuoso

Talent Edge Recruiting; Richardson (TX); Hybrid; USD 59,000 - 83,000; Full time

Benefits offered by this job

Medical, dental, and vision benefits

401(k) retirement plan with company-m匹

Life insurance

Overtime opportunities

Hybrid work schedule (Tue–Thu onsite,

Career advancement opportunities

Job summary

Talent Edge Recruiting is seeking an experienced Analog IC Layout Design Engineer in Richardson, TX. This hybrid role requires expertise in full-custom analog/mixed-signal layout, Cadence Virtuoso/VXL, and Calibre, with exposure to FinFET/GAA processes (7nm–3nm).

You will develop layouts for PLLs, SerDes, ADCs, and DACs, collaborating with design engineers to optimize performance, area, power, and reliability. U.S. citizens or green-card holders preferred.

Qualifications

• 3+ years of hands-on experience in full-custom analog, RF, or mixed-signal IC layout.
• Strong proficiency with Cadence Virtuoso/VXL and Calibre (DRC, LVS, ERC).
• Experience with advanced FinFET/GAA process technologies (7nm/4nm/3nm).
• Experience laying out PLLs, SerDes, ADCs, and DACs in analog/mixed-signal blocks.
• Solid understanding of matching, shielding, guard rings, and latch-up.
• Knowledge of electromigration, IR drop, and crosstalk effects.
• Experience with hierarchical layout construction and DFM methodologies.
• Strong analytical, debugging, and communication skills.
• Bachelor's degree in Electrical Engineering; equivalents considered for experienced candidates.

Responsibilities

• Perform full-custom layout and physical verification of analog, RF, and mixed-signal ICs.
• Develop layouts for PLLs, SerDes, ADCs, DACs, and RF components.
• Work with FinFET/GAA technologies (7nm, 4nm, 3nm).
• Utilize Cadence Virtuoso/VXL and Calibre for layout and verification (DRC/LVS/ERC).
• Apply advanced layout techniques to optimize matching, shielding, and latch-up prevention.
• Address layout-dependent issues such as electromigration, IR drop, RC delay, and crosstalk.
• Contribute to hierarchical layouts and DFM-based design for manufacturability.
• Collaborate with design engineers to optimize performance, area, power, and reliability.
• Support verification from blocks to top-level integration.

Skills

Analog IC layout

Cadence Virtuoso/VXL

Calibre DRC/LVS/ERC

FinFET/GAA process knowledge

PLL/SerDes/ADCs/DACs layout

Matching/Shielding/Latch-up

EM/IR drop/Crosstalk awareness

Hierarchical layout/DFM

Communication skills

Education

Bachelor's degree in Electrical Engineering

Associate degree or technical training with layout experience

Tools

Cadence Virtuoso/VXL

Calibre

Job description

Talent Edge Recruiting is seeking an experienced Analog IC Layout Design Engineer in Richardson, TX. This hybrid role requires expertise in full-custom analog/mixed-signal layout, Cadence Virtuoso/VXL, and Calibre, with exposure to FinFET/GAA processes (7nm–3nm).

You will develop layouts for PLLs, SerDes, ADCs, and DACs, collaborating with design engineers to optimize performance, area, power, and reliability. U.S. citizens or green-card holders preferred.