HW Design Verification Engineer (Junior / Senior)

ASAL TECHNOLOGIES; Palestine (TX); On-site; USD 90,000 - 130,000; Full time

Job summary

ASAL TECHNOLOGIES seeks Hardware Design Verification Engineers to verify complex digital designs and deliver robust silicon using advanced methodologies. Collaborate with architects, design engineers, software teams, and CAD specialists to execute comprehensive verification plans and test suites for cutting-edge hardware.

The role welcomes junior to senior candidates, with responsibilities spanning verification strategy, testbench development, and regression improvements.

Qualifications

• Fresh graduates or more experienced engineers welcomed; strong fundamentals in digital design are required.

Responsibilities

• Develop and execute verification plans based on design specifications.
• Build and maintain testbenches using Verilog, SystemVerilog, UVM, and Specman eRM.
• Create and run simulation test cases to verify functionality and performance.
• Identify, debug, and track design and verification issues.
• Collaborate with design, architecture and firmware teams.
• Analyze simulation results, coverage reports and debug failures.
• Ensure high functional and code coverage.

Skills

Analytical thinking

Teamwork

Problem solving

Willingness to learn

Education

B.Sc./M.Sc. in Electrical Engineering or related field

Tools

Verilog

SystemVerilog

UVM

Specman eRM

VCS

Xcelium

Job description

We are looking for passionate talented and detail-oriented Hardware Design Verification Engineers to join our growing hardware team In this role you will be responsible for verifying complex digital designs ensuring the delivery of robust reliable and high-quality silicon through advanced verification methodologies You will collaborate closely with architects design engineers software teams and CAD specialists to develop and execute comprehensive verification plans testbenches and test suites for our advanced hardware products This position is open to both entry-level junior and experienced senior candidates The scope of responsibility will vary depending on experience

Key Responsibilities For All Levels

• Develop and execute verification plans based on design specifications
• Build and maintain testbenches using Verilog Specman eRM SystemVerilog and UVM
• Create and run simulation test cases to verify functionality and performance
• Identify debug and track design and verification issues
• Collaborate closely with design architecture and firmware teams
• Analyze simulation results coverage reports and debug failures
• Ensure high functional and code coverage

Additional Responsibilities Senior Level

• Define verification strategy and architecture for complex IPs or subsystems
• Lead verification efforts and mentor junior engineers
• Drive coverage closure and verification sign-off
• Improve and optimize verification flows and methodologies
• Contribute to automation regression infrastructure and CI flows
• Participate in design reviews and provide feedback for verification readiness

For Junior Candidates

• Fresh graduates/undergraduates who will graduate this semester are welcome to apply as well.B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or related field.
• Basic understanding of digital design fundamentals (RTL, FSMs, pipelines).
• Familiarity with Verilog/SystemVerilog.
• Knowledge of object-oriented programming (OOP) and scripting languages such as Python, Perl, or Shell.
• Solid understanding of data structures and algorithms
• Strong analytical and problem-solving skills.
• Willingness to learn and grow in verification methodologies.
• Good communication and teamwork skills
• Ability to work independently and think critically to solve complex problems

For Experienced Candidates

• 3+ years of experience in Design Verification.
• Strong hands-on experience with Specman, SystemVerilog and UVM.
• Proven experience in testbench development and debugging.
• Solid understanding of verification methodologies and coverage techniques.
• Experience with protocol-based verification (e.g., AMBA AXI, PCIe) advantage.
• Familiarity with tools such as VCS, Xcelium, or similar simulators.
• Experience in scripting languages (e.g., Python, Perl, or Tcl) advantage.
• Exposure to Continuous Integration (CI) workflow and version control systems (e.g., Git).