HBM SoC RTL Design Intern

Micron Technology, Inc; Folsom (CA); On-site; USD 54,000 - 69,000; Full time

Benefits offered by this job

Medical/Dental/Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc in California is seeking a SoC Design Engineer Intern to contribute to the design and integration of next-generation HBM logic die within the Heterogeneous Integration Group.

You will collaborate with architecture, verification, physical design, firmware, and product teams, gain hands-on RTL/Verilog experience, and support pre- and post-silicon activities while exploring AI-driven workflows.

Qualifications

• Currently pursuing a Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. Cannot graduate prior to December 2027, and must be available for a 6‑month internship.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL‑to‑GDS flow, including synthesis, static timing analysis, and develop sign‑off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

Responsibilities

• Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die.
• Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic).
• Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations.
• Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi‑functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Skills

SystemVerilog/Verilog

RTL-to-GDS flow

Python scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology, Inc in California is seeking a SoC Design Engineer Intern to contribute to the design and integration of next-generation HBM logic die within the Heterogeneous Integration Group.

You will collaborate with architecture, verification, physical design, firmware, and product teams, gain hands-on RTL/Verilog experience, and support pre- and post-silicon activities while exploring AI-driven workflows.