HBM SoC RTL Design Architect

Micron; Folsom (CA); On-site; USD 121,000 - 247,000; Full time

Job summary

Micron Technology, a world leader in memory solutions, seeks an experienced RTL engineer to design and implement SoC‑level RTL blocks for HBM die. You will integrate controllers, NOC, MBIST, and other IP, translating architectural specs into high‑quality RTL and driving robust integration.

You will collaborate with SoC architects across clocking, reset, power intent, and configuration infrastructure, supporting pre‑ and post‑silicon validation and contributing to design reviews.

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, or related field with at least 3 years' experience.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with RTL-to-GDS flow, including synthesis and timing analysis.
• Familiarity with Cadence, Synopsys, and Siemens EDA tools.
• Programming or scripting experience (Python, TCL, Perl, or shell).

Responsibilities

• Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die.
• Integrate internal and third‑party IP (controllers, microcontrollers, NOC, RAS, MBIST, interfaces, buffers, PHY‑adjacent logic).
• Collaborate with SoC architects to translate specs into RTL implementations.
• Participate in SoC‑level integration activities including clocking, reset, power, and configuration infrastructure.
• Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate cross‑functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing.

Skills

SystemVerilog/Verilog

RTL design

EDA tools familiarity

Scripting (Python TCL Perl)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology, a world leader in memory solutions, seeks an experienced RTL engineer to design and implement SoC‑level RTL blocks for HBM die. You will integrate controllers, NOC, MBIST, and other IP, translating architectural specs into high‑quality RTL and driving robust integration.

You will collaborate with SoC architects across clocking, reset, power intent, and configuration infrastructure, supporting pre‑ and post‑silicon validation and contributing to design reviews.