HBM SoC Physical Design Engineer Intern

Micron Technology, Inc.; Folsom (CA); On-site; USD 110,208,000 - 144,648,000; Full time

Job summary

Micron Technology, Inc. is seeking an SoC Physical Design Intern to support the HBM team in implementing high-bandwidth memory designs for AI and HPC applications.

You will work with experienced engineers on floorplanning, placement, clock tree synthesis, routing, and physical verification. Gain hands-on experience with timing analysis, signoff flows, automation tooling in Python, Tcl, and shell, and collaborate across RTL, verification, and architecture to deliver memory products powering

Qualifications

• 0–2 years of ASIC/physical design experience through internships, coursework, or research.
• Master's student in Electrical or Computer Engineering pursuing relevant specialization.
• Knowledge of ASIC flow concepts: synthesis, P&R, STA, and physical verification.

Responsibilities

• Support physical implementation of SoC blocks: floorplanning, placement, RTL-to-GDSII basics.
• Analyze timing, power, area, congestion; assist with timing closure and debugging.
• Develop automation tools and scripts using Python, Tcl, and shell.
• Collaborate with RTL, verification, and architecture teams; present findings.

Skills

Python

Tcl

Shell scripting

AI tools

Timing analysis

Problem solving

Team collaboration

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Cadence Innovus

Synopsys PrimeTime

Synopsys ICC2

Calibre

Job description

Micron Technology, Inc. is seeking an SoC Physical Design Intern to support the HBM team in implementing high-bandwidth memory designs for AI and HPC applications.

You will work with experienced engineers on floorplanning, placement, clock tree synthesis, routing, and physical verification. Gain hands-on experience with timing analysis, signoff flows, automation tooling in Python, Tcl, and shell, and collaborate across RTL, verification, and architecture to deliver memory products powering