Senior ASIC Design Engineer

Ethan Alexander Group; San Francisco (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Ethan Alexander Group is seeking an ASIC Design Engineer in San Francisco to define and bring up FPGA platforms for pre-silicon validation and software development. You will map ASIC RTL to FPGA and design logic from high level specifications.

The role requires strong debugging and analytical skills, with 5+ years in the field and BS in EE (MS preferred). Proficiency in Python or C/C++ and familiarity with lab equipment are essential.

Qualifications

• Minimum of 5 years of relevant experience.
• Python or C/C++ programming experience.
• Ability to write and analyze the completeness of constraints.
• Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters.
• Strong analytical and debugging skills.
• BS in Electrical Engineering or equivalent required, MS preferred.

Responsibilities

• Define and bring up FPGA platforms for pre-silicon validation and software development.
• Map ASIC RTL to FPGA while minimizing code base differences.
• Create and execute test plans for validating SoC functionality and performance.
• Resolve challenging system level issues that span multiple disciplines.
• Design logic starting from specification or high level feature description.

Skills

Python

C/C++

Constraint writing

Analytical skills

Debugging

Education

BS in Electrical Engineering

MS preferred

Tools

Vivado tool chain

Logic analyzers

Oscilloscopes

Multimeters

Job description

ASIC Design Engineer

Responsibilities

• Define and bring up FPGA platforms for pre-silicon validation and software development
• Map ASIC RTL to FGPA while minimizing code base differences
• Create and execute test plans for validating SoC functionality and performance
• Resolve challenging system level issues that span multiple disciplines
• Design logic starting from specification or high level feature description

Requirements

• Minimum of 5 years of relevant experience.
• Scripting or programming experience in Python or C/C++
• Ability to write and analyze the completeness of constraints
• Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters
• Strong analytical and debugging skills
• BS in Electrical Engineering or equivalent required, MS preferred

Nice to Have

• Familiarity with Xilinx FPGA's and Vivado tool chain
• Experience with validating and debugging low-power wireless systems
• Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)
• Knowledge of wireless protocols (e.g. Bluetooth Low Energy)