Hardware Engineer, AI Accelerator Power Design

Meta; Austin (TX); On-site; USD 170,000 - 230,000; Full time

Job summary

The ARD team at Meta designs accelerator reference platforms for Meta's AI hardware roadmap. This role owns the board-level power delivery system end to end for multi-kilowatt accelerator modules, including DC/DC topology, PDN, and lab correlation.

You will collaborate with ASIC, hardware platform, thermal, SI/PI, and mechanical teams, coordinate with external partners and ODMs, and drive designs from concept through production with strong emphasis on reliability and performance in dense

Qualifications

• BS in Electrical Engineering or equivalent; 8+ years hardware power design experience.
• Multiple complex power designs taken to volume production with ownership of both converter design and the board-level power delivery path.
• DC/DC power electronics design: topology, component selection, regulation scheme, bring-up and validation.
• Efficiency design practice in high-power systems under space and thermal constraints.
• Deep hands-on PCB physical design: PDN design, power planes, stack-up, placement, and layout.
• Power integrity modeling and simulation with lab correlation.
• Experience with high-current, low-voltage rails and decoupling strategies for large digital loads.
• Proficiency with schematic capture and layout tools; PI/PDN simulation tools (e.g., Ansys SIwave/Q3D, Cadence Sigrity).
• Lab proficiency with oscilloscopes, electronic loads, thermal imaging.

Responsibilities

• Own the module power delivery system end to end: DC/DC topology and component selection, regulation scheme, and the PCB power delivery network.
• Set power specifications and efficiency targets for high-power ASIC loads; make component and architecture choices against space, thermal, cost, and production-reliability constraints.
• Own PCB physical design of the power path: PDN architecture and optimization, power plane design, stack-up definition, placement analysis, and power circuit layout best practices.
• Define and close power integrity targets through modeling and simulation (DC IR drop, AC impedance, transient response), and correlate simulation against lab measurements.
• Partner with ASIC teams on package/board co-design, including socket and interposer power path, current density, and on-die vs. on-board decoupling allocation.
• Lead board bring-up, validation, and debug of power rails; define measurement methodology for high-current, low-voltage rails.
• Drive design reviews with ODM/CM partners; establish layout and DFx best practices adopted across ARD.
• Explore and develop leading-edge DC/DC and power delivery technologies (e.g., vertical power delivery, near-die power modules) with industry partners.
• Contribute to design guidelines, review checklists, and tooling that raise the quality bar across ARD.

Skills

Power electronics

PCB design

Power integrity

DC/DC design

High-current design

Schematic capture

Lab measurement

Vendor management

DFx processes

Thermal management

Education

BS in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Ansys SIwave

Cadence Sigrity

Q3D

PCB layout tools

Job description

About

The ARD team designs accelerator reference platforms for Meta's AI hardware roadmap. This role owns the board-level power delivery system end to end for multi-kilowatt accelerator modules — DC/DC converter design and the PCB power delivery network, from topology and component selection through PDN architecture, stack-up, placement, layout, power integrity simulation, and lab correlation. You will work closely with ASIC, HW platform, thermal, SI/PI, and mechanical teams to co-design the power path, and directly with top-tier external partners and ODMs to drive designs from concept through production.

Responsibilities

• Own the module power delivery system end to end: DC/DC topology and component selection, regulation scheme, and the PCB power delivery network
• Set power specifications and efficiency targets for high-power ASIC loads; make component and architecture choices against space, thermal, cost, and production-reliability constraints
• Own PCB physical design of the power path: PDN architecture and optimization, power plane design, stack-up definition, placement analysis, and power circuit layout best practices
• Define and close power integrity targets through modeling and simulation (DC IR drop, AC impedance, transient response), and correlate simulation against lab measurements
• Partner with ASIC teams on package/board co-design, including socket and interposer power path, current density, and on-die vs. on-board decoupling allocation
• Lead board bring-up, validation, and debug of power rails; define measurement methodology for high-current, low-voltage rails
• Drive design reviews with ODM/CM partners; establish layout and DFx best practices adopted across the broader team
• Explore and develop leading-edge DC/DC and power delivery technologies (e.g., vertical power delivery, near-die power modules) with industry partners
• Contribute to design guidelines, review checklists, and tooling that raise the quality bar across ARD

Minimum Qualifications

• BS in Electrical Engineering or equivalent, plus 8+ years of hardware power design experience (MS + 6 years, or PhD + 4 years)
• Multiple complex power designs taken to volume production, with ownership of both the converter design and the board-level power delivery path
• DC/DC power electronics design experience: specification and requirement setting, topology and component selection, regulation scheme definition, and bring-up/validation/troubleshooting
• Demonstrated efficiency design practice in high-power systems: setting efficiency targets, component selection for efficiency, and trade-offs under space and thermal limitations
• Deep hands-on PCB physical design experience: PDN design and optimization, power plane design, stack-up definition, placement analysis, and power circuit layout best practices
• Power integrity expertise: circuit modeling and simulation used to drive design iteration, with proven simulation-to-lab closure, and knowledge of where/how to measure power effectively in DC/DC designs
• Experience with high-current, low-voltage rails and the decoupling/noise strategy for large digital loads (ASIC, SoC, GPU, or similar)
• Proficiency with schematic capture and layout tools, and PI/PDN simulation tools (e.g., Ansys SIwave/Q3D, Cadence Sigrity, or equivalent)
• Lab proficiency: oscilloscopes, electronic loads, thermal imaging, and measurement techniques appropriate to high-current power rails
• Track record operating independently on ambiguous problems and driving cross-functional efforts to resolution without guidance Experience supporting multiple complex programs in parallel, balancing competing schedules and priorities across concurrent design cycles
• Experience with thermal/mechanical co-design in dense liquid-cooled or air-cooled modules
• Experience with 1kW+ accelerator or ASIC-class power delivery, including 48V architectures
• Experience defining team-wide design standards, review processes, or automation
• Experience driving vendor and ODM development cycles end to end, including technology roadmap engagement with silicon and passive component suppliers
• Experience with vertical power delivery, power modules integrated near-die, or backside power delivery concepts
• Awareness of power delivery technology trends for 1kW-and-beyond ASICs