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HCL Technologies Limited in the United States seeks a Group Technical Architect with 8–14 years of experience to define micro-architecture specifications for high-performance, low-power digital blocks and subsystems, and to oversee full-chip RTL integration. You will lead a team of 5–6 leads, manage two projects concurrently, and interact with clients across geos.
Strong RTL, ASIC/SoC flows, synthesis, timing, and IP integration experience are essential.
Requisition ID188591-Posted11/02/2026
Candidates with 8 to 14 years experience is mandatoryExperience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems.Experience in Full chip RTL integration
Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc.Experience in RTL SynthesisScripting experienceExperience integrating IP's like PCIe, DDR, Ethernet etc.
Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there.Expected to handle minimum 2 projects simultaneouslyExperience in handling and interacting with clients across different Geos.Excellent communication skills are mandatory.