Graduate Analog IC Design Engineer (RadHard IP)

Infineon Technologies; Andover (MA); On-site; USD 81,000 - 90,000; Full time

Job summary

Infineon Technologies in Andover, MA seeks a Master’s-educated Electrical Engineer to design and verify analog/mixed-signal IP blocks for radiation-hardened power management. You will collaborate with layout and verification teams, using Cadence tools, to ensure robust RadHard performance across process corners.

Graduates in Fall 2026 or Spring 2027 with strong fundamentals in analog/mixed-signal design and internship exposure are encouraged.

Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or related field preferred.
• Strong analog/mixed-signal circuit design fundamentals.
• Exposure to backend semiconductor processing or radiation-hardened design environments preferred.
• Hands-on Cadence design tool experience for schematic capture and simulation.

Responsibilities

• Define, design, and validate analog/mixed-signal IP blocks for radiation-hardened power management applications.
• Partner with layout engineers to ensure optimal block layout and RadHard performance.
• Oversee behavioral modeling of analog/mixed-signal IP blocks across process corners.
• Document design architecture, implementation strategies, and testing methodologies.
• Participate in bottom-up and top-level IC verification within a structured design flow.
• Assist lab and test engineers in validation and characterization of mixed-signal IP in hardware.

Skills

Strong communication

Collaborative

Self-driven

Education

Master's degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Cadence Spectre

Cadence ADE

Job description

Infineon Technologies in Andover, MA seeks a Master’s-educated Electrical Engineer to design and verify analog/mixed-signal IP blocks for radiation-hardened power management. You will collaborate with layout and verification teams, using Cadence tools, to ensure robust RadHard performance across process corners.

Graduates in Fall 2026 or Spring 2027 with strong fundamentals in analog/mixed-signal design and internship exposure are encouraged.