GPU Physical Design Engineer

Apple Inc.; Cupertino (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Apple Inc. in Cupertino, CA is seeking a senior professional to design and implement next-generation GPU PD flows. You will drive physical design from RTL to tapeout, coordinating with FE teams and leading place-and-route efforts to optimize performance, power and area.

The role involves pioneering PD methodologies, addressing cross-functional design issues, and delivering world-class GPU implementations on cutting-edge technology nodes.

Qualifications

• Experience with industry standard physical Implementation tools and PPA optimization flows.
• Experience with TCL, Perl or Python scripting.
• BS + 10 years of relevant experience.

Responsibilities

• Work closely with FE team to understand chip architecture and drive physical aspects early in design cycle.
• Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.
• Be focal point for place and route drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work.

Skills

PPA optimization

Scripting: TCL/Perl/Python

Education

BS degree + 10 years experience

Tools

ASIC/PD tools

Job description

Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions! Joining this group means crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands‑on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to tapeout.

Description

In this role, you will:- Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.- Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.- Drive best in class PD construction and optimization recipes for performance, power and Area (PPA).- Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress.- Work on cutting edge designs in the latest technology nodes.- Be focal point for place and route drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.- Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.- Work cross-functionally to ensure delivery of best in class physical implementations geared towards world class products

Minimum Qualifications

• Experience with industry standard physical Implementation tools and PPA optimization flows
• Experience with TCL, Perl or Python scripting
• BS + 10 years of relevant experience

Preferred Qualifications

• We value proven ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
• Work with FE teams to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback.
• Use design knowledge and innovative physical construction and optimization flows to push performance, power, and Area (PPA) of GPU designs.
• Experience with multi-voltage, power gated and power retention will be an advantage.
• Your practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset.
• Showcase your experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
• Track record of applying creative thinking to strategically solve problems that have impact for a project, group, or organization.
• Your depth of expertise with large GPU designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies will serve you well.
• From a CAD tool perspective, experience creating and analyzing floorplanning tools, P&R flows, static timing and Physical Design Verification Flows is required.
• Experience with various process related design issues including Design for Yield and manufacturability, multi Vt strategies and thermal Management.
• Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class GPU designs.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.