GPU Electrical Analysis Engineer

Apple Inc.; Santa Clara (CA); On-site; USD 190,000 - 260,000; Full time

Job summary

Apple Inc. in Santa Clara, CA is seeking a GPU Electrical Analysis engineer within the Silicon Technologies group to design power grids and ensure the best balance between PI targets and PNR performance.

You will define on-die topologies, wake-up schemes, and in-rush control while collaborating on bump map, RDL routing, and package design optimization. You will develop test structures and methodologies for electrical analysis, perform Power Integrity, EM, and ESD analyses, and drive back-end

Qualifications

• Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks.
• Experience with global power integrity tools (e.g. Redhawk, Voltus).
• Strong understanding of PD/Power distribution in large SoCs.

Responsibilities

• Design power grid specifications balancing PI targets with PNR and area.
• Define on-die power switch topology, wake-up schemes, and in-rush control.
• Collaborate on bump map, RDL routing, and package design optimization.
• Develop test structures, automation, and methodologies for electrical analysis.
• Perform Power Integrity, EM, ESD analyses and drive design solutions.
• Communicate needs with PD and Electrical Analysis across teams.

Skills

Power integrity

Electromigration

Static IR

Dynamic voltage drop

Redhawk

Voltus

On-die PD

Bump planning

RDL routing

ASIC integration

Floorplanning

Timing verification

SPICE simulation

Education

Bachelor's degree in Electrical Engineering

Tools

Redhawk

Voltus

Job description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next‑generation, high‑performance, power‑efficient GPU. You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices! Together, you and your team will enable our customers to do all the things they love with their devices. This exciting role requires a mix of strategic engineering along with hands‑on, technical work! You will be responsible for realizing the complete electrical analysis closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration.

Description

As a GPU Electrical Analysis engineer, you will work closely with the Physical Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA). You will be involved with the definition of on‑die power switch topology, wake‑up schemes, and in‑rush control. Collaboration with internal teams to drive bump map, custom RDL routing, and package design/optimization will be required. You will develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges. You will perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions. Finally, you will communicate and drive the needs of PD and Electrical Analysis with multi‑functional teams that will enable achieving the goals of the back‑end design for the project.

Minimum Qualifications

• BS + 3 years of relevant experience
• Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks.
• Experience with global power integrity tools (e.g. Redhawk, Voltus).

Preferred Qualifications

• Experience with on‑die high frequency power delivery, and exposure to off‑die concepts and models.
• Experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios.
• Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Background with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies.
• Track record in solving complex PD and multi‑functional problems, getting results directly and or directing a team of engineers to innovate and execute on world class GPU designs.
• Circuit design and simulation background a plus, but not required.
• Experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification Flows.

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