Global System-Level Test Program Lead

Broadcom; Irvine (CA); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Medical

Dental

Vision

401K

ESPP

EAP

Paid holidays

Paid leave

Job summary

Broadcom in Irvine, CA is seeking a System Level Test Program Manager to own SLT program execution for multiple XPU customer programs across a distributed US-Asia footprint, balancing delivery with innovation. You will manage schedules, yield, and cost while partnering with Asia test operations and leading on-site production activities.

Responsibilities include weekly status reviews, risk mitigation, translating customer specs into SLT plans, coordinating cross‑timezone teams, and occasional

Qualifications

• Bachelor's degree and 12+ years of related experience.
• 9+ years in semiconductor test engineering or test operations (SLT, probe test, or production test).
• 3-5 years in program or operations leadership (with schedule, cost, or quality accountability).
• Hands-on expertise in ATE programming, test methodology, yield debugging, and SLT tool flows.
• Demonstrated success shipping 2+ high-volume programs from silicon bring-up through ramp.
• Experience working with cross-geographic or distributed teams; comfort with asynchronous collaboration and time zone management.
• Strong project management discipline: risk tracking, escalation, forecasting, decision documentation.
• Proficiency with test data analysis, yield correlation, and statistical methods.
• Willingness and ability to travel internationally (Asia production sites).
• Excellent communication skills with engineers, operations teams, customers, and leadership.

Responsibilities

• Own end-to-end SLT execution for multiple concurrent XPU programs through silicon bring-up, production ramp, and sustained 100% volume operations.
• Drive weekly program status, risk tracking, and customer commitments; escape blockers to Senior Management within 24 hours with recommended mitigation.
• Translate customer test specifications, quality gates, and margining requirements into actionable SLT plans; own electrical test coverage sign-off and escape rate targets.
• Manage portfolio prioritization when programs compete for resources (equipment, site capacity, engineer time); present trade-off options and risks to director for conflict resolution.
• Conduct customer program reviews, status updates, and escalation communication; own SLT portion of customer commitments.
• Travel to Asia production sites couple times a year to manage test floor execution, resolve operational blockers, and ensure quality/schedule adherence.
• Forecast SLT capacity requirements, drive equipment utilization optimization, and manage shift planning across US R&D and Asia production sites.
• Partner with Ops manager on sustained production operations.
• Establish SLT quality gates, data integrity audits, and escalation protocols for Asia production sites.
• Drive equipment maintenance scheduling, spare parts inventory management, and tooling readiness to maximize SLT test floor uptime and minimize operational downtime.
• Evaluate and pilot new test techniques (advanced margining, Vmin stress, multi-site protocols) in partnership with Design/DFT teams.
• Lead transition of new test methodologies from R&D (US) to production (Asia); drive pilot design, runoff, and full deployment.
• Influence ATE equipment roadmap and automation tooling; assess new equipment investments and ROI for SLT operations.
• Mentor engineers on advanced test methodologies and drive capability growth in distributed team.
• Contribute to post-silicon debug and yield correlation analysis; own SLT test-related root cause investigations.
• Identify, track, and prioritize risks across schedule, yield, capacity, and equipment; assess risk working with owners and target closure.
• Lead root-cause analysis on yield misses, test escapes, and schedule delays; own corrective action closure and prevention planning.
• Partner with Design/DFT on testability and early-silicon yield correlation; surface test bottlenecks before they cascade.
• Coordinate with Manufacturing and Logistics on device staging, test scheduling, and shipment readiness.
• Work with Quality/Reliability on escape analysis and early-life failure investigation.
• Drive SLT yield improvement initiatives and Defective Parts Per Million (DPPM) reduction targets by partnering with test, design, and manufacturing teams to drive continuous quality enhancements

Skills

Program management

Semiconductor test

Test methodology

ATE programming

Yield debugging

Cross-timezone collaboration

Education

Bachelors degree

Tools

Test equipment

Test data analysis tools

Job description

Broadcom in Irvine, CA is seeking a System Level Test Program Manager to own SLT program execution for multiple XPU customer programs across a distributed US-Asia footprint, balancing delivery with innovation. You will manage schedules, yield, and cost while partnering with Asia test operations and leading on-site production activities.

Responsibilities include weekly status reviews, risk mitigation, translating customer specs into SLT plans, coordinating cross‑timezone teams, and occasional