FPGA Verification Engineer - 100G+ & UVM Expert

Amazon Web Services (AWS); Arlington (VA); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Development Center U.S., Inc. in Arlington, VA seeks a Verification Engineer to develop UVM/SystemVerilog testbenches for 100G+ FPGA/ASIC designs and to architect scalable verification environments.

You will create verification plans, scoreboards, and checkers, collaborate with RTL designers, debug simulation, and support hardware validation. US Citizenship and TS/SCI clearance with polygraph is required.

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or a related field.
• 3+ years of non-internship design or architecture experience.
• 4+ years of non-internship professional verification experience using SystemVerilog and/or UVM.
• 2+ years of experience verifying digital logic designs (FPGA or ASIC).
• Current, active US Government Security Clearance of Top Secret with SCI eligibility or above.

Responsibilities

• Develop UVM/SystemVerilog testbenches to verify custom RTL designs and third-party IP integrations for 100G+ solutions.
• Create and execute verification plans including functional coverage models, assertions, and constrained-random stimulus.
• Collaborate with design engineers to understand specifications and identify verification requirements and corner cases.
• Develop bus functional models, scoreboards, and checkers for complex interface protocols.
• Debug simulation failures, analyze waveforms, and drive issues to root cause resolution.
• Support FPGA-in-the-loop and hardware validation efforts by developing test sequences and diagnostic utilities.

Skills

SystemVerilog

UVM

Verification

Education

Bachelor's degree in Electrical or Communications Engineering or related field

Master's degree in Electrical or Communications Engineering or related field

Tools

Vivado

VCS/Cadence Xcelium

Job description

Amazon Development Center U.S., Inc. in Arlington, VA seeks a Verification Engineer to develop UVM/SystemVerilog testbenches for 100G+ FPGA/ASIC designs and to architect scalable verification environments.

You will create verification plans, scoreboards, and checkers, collaborate with RTL designers, debug simulation, and support hardware validation. US Citizenship and TS/SCI clearance with polygraph is required.