FPGA Silicon Design Engineer

Altera; San Jose (CA); On-site; USD 142,000 - 228,000; Full time

Job summary

Join a leading semiconductor company as an FPGA Silicon Design Engineer. You will develop logic designs and simulations for FPGAs, ensuring high-performance and power-efficient designs. The role requires extensive experience in hardware design and programming languages, with opportunities for growth and competitive compensation.

Benefits

Medical insurance

Vision insurance

401(k)

Qualifications

• Must have 9+ years of experience with a Bachelor's or 6+ years with a Master's.
• In-depth knowledge of industry-standard tools for front-end design.

Responsibilities

• Develops logic design and simulation for FPGAs.
• Creates prototypes and specifies system requirements.
• Reviews verification plans to ensure design correctness.

Skills

Python

RTL

System Verilog

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

Synthesis

STA

Spyglass-based checks

Job description

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This range is provided by Altera. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$142,600.00/yr - $227,800.00/yr

Job Description:

Join Altera as a FPGA Silicon Design Engineer! The FPGA Silicon Design Engineer develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

Other Responsibilities Include But Are Not Limited To

• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Creates prototypes, simulates models, and specifies systems requirements.
• Prepares and designs logic diagrams and codes for implementing system design and test specifications.
• Delivers software models for device level bring up, including user visible functionality, timing, and power.
• Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Salary Range

Our compensation reflects the cost of labor within the US market. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$142,600-$227,800K

Minimum Qualifications

The candidate must have a Bachelor's Degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience - OR- a Master's Degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6+ years of industry work experience -OR- a PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4+ years of related work experience in:

• Programming languages such as Python, RTL, and System Verilog.
• Understanding of hardware design, including logic design, state machines, control units, processor sub-systems, and network on chips.
• In-depth knowledge of industry-standard tools and flows for front-end design, including synthesis, STA, Spyglass-based checks, and power domains.

Preferred Qualifications

• Experience with AES/SHA, as well as compression and decompression algorithms.
• Knowledge of Network on Chips and Control Processors.

Primary Location:

San Jose

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

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Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

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