FPGA Placement Engineer – Optimize Timing & QoR

Altera; San Jose (CA); On-site; USD 149,100 - 215,900; Full time

Benefits offered by this job

Challenging algorithmic problems

Collaborative environment with top teams

Incentive opportunities based on performance

Job summary

Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role is pivotal in developing and optimizing FPGA placement algorithms, directly impacting design performance and quality.

The ideal candidate will have at least 6 years of relevant experience and proficiency in C/C++. This position offers a competitive salary range of $149.1K-$215.9K.

Join our innovative team to impact the future of programmable technologies!

Qualifications

• 6+ years of experience in FPGA/ASIC CAD or EDA tools.
• Experience with algorithms and data structures (optimization, graph theory, heuristics).
• Experience with analytical placement and optimization techniques.

Responsibilities

• Design and implement FPGA placement algorithms.
• Contribute to the end-to-end FPGA compilation flow.
• Analyze placement quality and drive improvements.

Skills

Algorithms and data structures

C/C++ proficiency

FPGA/ASIC CAD experience

Optimization techniques

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

FPGA toolchains (e.g., Quartus, Vivado)

Job description

Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role is pivotal in developing and optimizing FPGA placement algorithms, directly impacting design performance and quality.

The ideal candidate will have at least 6 years of relevant experience and proficiency in C/C++. This position offers a competitive salary range of $149.1K-$215.9K.

Join our innovative team to impact the future of programmable technologies!