FPGA Compiler (Placer) Engineer

Altera; San Jose (CA); On-site; USD 149,100 - 215,900; Full time

Benefits offered by this job

Challenging algorithmic problems

Collaborative environment with top teams

Incentive opportunities based on performance

Job summary

Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role is pivotal in developing and optimizing FPGA placement algorithms, directly impacting design performance and quality.

The ideal candidate will have at least 6 years of relevant experience and proficiency in C/C++. This position offers a competitive salary range of $149.1K-$215.9K.

Join our innovative team to impact the future of programmable technologies!

Qualifications

• 6+ years of experience in FPGA/ASIC CAD or EDA tools.
• Experience with algorithms and data structures (optimization, graph theory, heuristics).
• Experience with analytical placement and optimization techniques.

Responsibilities

• Design and implement FPGA placement algorithms.
• Contribute to the end-to-end FPGA compilation flow.
• Analyze placement quality and drive improvements.

Skills

Algorithms and data structures

C/C++ proficiency

FPGA/ASIC CAD experience

Optimization techniques

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

FPGA toolchains (e.g., Quartus, Vivado)

Job description

About Altera

At Altera™, the world’s largest pure‑play FPGA solutions provider, our independence enables focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets such as AI, cloud, networking, and edge.

Position Overview

Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.

Key Responsibilities

• Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Contribute to the end‑to‑end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
• Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
• Develop and refine timing‑aware placement strategies to support high‑frequency, performance‑critical designs.
• Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
• Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
• Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
• Experience in algorithms and data structures (optimization, graph theory, heuristics).
• Experience with placement algorithms or physical design flows.
• Proficiency in C/C++ and software engineering best practices.
• Experience with analytical placement, simulated annealing, partitioning, clustering, and other placement techniques.
• Experience with timing‑driven and congestion‑driven optimization.
• Background in ASIC or FPGA physical design methodologies.
• Experience solving large‑scale optimization problems with high performance and scalability requirements.

Preferred Qualifications

• Experience with FPGA toolchains (e.g., Quartus, Vivado).
• Knowledge of FPGA architectures and interconnect fabrics.
• Familiarity with routing and timing closure techniques.
• Experience with parallel or distributed algorithms for EDA tools.
• Scripting experience (e.g., Python, Tcl) for tooling and automation.

Job Type & Location

Job Type: Regular

Shift: Shift 1 (United States of America)

Primary Location: San Jose, California, United States

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

Work on core compiler technology that directly impacts FPGA performance and usability.

Solve challenging algorithmic problems at scale.

Collaborate with world‑class teams across architecture, silicon, and software.

Salary

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149.1K-$215.9KUSD

Compliance

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.