FPGA Development Tools Engineer – Synthesis

191 Altera Corporation; San Jose (CA); On-site; USD 149,100 - 215,900; Full time

Job summary

191 Altera Corporation, located in San Jose, California, seeks a skilled FPGA Development Tools Engineer focused on optimizing synthesis algorithms and enhancing FPGA compilation technology. In this role, you will play a crucial part in transforming RTL designs into efficient hardware implementations, directly impacting performance and design quality.

The ideal candidate will have over 6 years of experience in FPGA/ASIC design and strong hands-on skills in RTL design and synthesis flows. This position offers an excellent salary range and benefits based on performance.

Qualifications

• 6+ years of experience in FPGA/ASIC design or EDA tools.
• Strong hands-on experience with RTL design and synthesis flows.
• Ability to analyze complex systems and develop scalable solutions.

Responsibilities

• Design and optimize synthesis algorithms for RTL to gate-level representation.
• Contribute to FPGA compiler flow integration.
• Develop internal tools and automate synthesis flows.

Skills

FPGA/ASIC design

Verilog/SystemVerilog or VHDL RTL design

C/C++ for tool development

Algorithms and data structures

Synthesis and optimization techniques

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Quartus

Vivado

Job description

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our FPGA compiler and development tools are central to enabling customers to efficiently design, optimize, and deploy complex hardware systems on advanced FPGA platforms.

Position Overview

We are seeking a FPGA Development Tools Engineer to join our Synthesis team, focused on advancing the next generation of FPGA compilation technology. In this role, you will develop and enhance synthesis capabilities that transform RTL designs into optimized hardware implementations, directly impacting performance, power, and area (PPA).

Key Responsibilities

• Design, implement, and optimize synthesis algorithms to convert RTL (Verilog/SystemVerilog/VHDL) into efficient gate-level representations.
• Contribute to the FPGA compiler flow, integrating synthesis with placement, routing, and timing (STA) stages.
• Improve quality of results (QoR) by optimizing performance, power, and area through synthesis-driven techniques.
• Develop tools and methodologies for analyzing and transforming complex RTL designs.
• Work closely with architecture, STA, placement, routing, and validation teams to ensure alignment across the toolchain.
• Analyze synthesis results, debug timing, logic structure, and mapping issues, and drive resolution.
• Develop internal tools, scripting, and automation to improve synthesis flows and productivity.

Qualifications

Required Qualifications:

• 6+ years of experience in FPGA/ASIC design, EDA tools, or related fields.
• Strong hands‑on experience with Verilog/SystemVerilog or VHDL RTL design and synthesis flows.
• Proficiency in C/C++ for tool development.
• Strong understanding of algorithms and data structures.
• Knowledge of logic synthesis and optimization techniques, FPGA or ASIC design flows (synthesis → P&R → STA), and timing‑driven design considerations.
• Ability to analyze complex systems and develop scalable, high‑performance solutions.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (PhD encouraged).

Preferred Qualifications:

• Experience with synthesis tools or FPGA toolchains (e.g., Quartus, Vivado).
• Knowledge of FPGA architectures (LUTs, DSPs, BRAM, interconnect).
• Familiarity with advanced optimizations (retiming, logic restructuring, resource sharing).
• Scripting experience (Python, Tcl).
• Background in compiler development or EDA algorithms.
• Experience working in large, distributed engineering teams.

Benefits

Pay range: $149.1K - $215.9K USD (Bay Area, California).

We also offer incentive opportunities that reward employees based on individual and company performance. Artificial intelligence is used for screening, assessment, and selection, and applicants must be eligible for any required U.S. export authorizations.

Job Details

Job Type: Regular.

Shift: Shift 1 (United States of America).

Primary Location: San Jose, California, United States.

Additional Locations: Not specified.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Why Join Altera

Build core synthesis technology for next-generation FPGA platforms, influence compiler architecture and performance at scale, and collaborate with world‑class engineers across silicon, architecture, and software.