FPGA Engineer PHASER

TensaCo Inc; San Francisco (CA); Vor Ort; USD 140.000 - 200.000; Vollzeit

Zusammenfassung

TensaCo Inc in San Francisco is looking for a mid-senior engineer to write gateware for PHASER modulators and translate detector samples into results. You will design FPGA logic and build interfaces with the rest of the system.

Responsibilities include verifying timing and throughput, working with Verilog/SystemVerilog or VHDL, and leveraging experience with high-speed serial interfaces and hardware verification.

Qualifikationen

• Experience with HDL languages (Verilog/SystemVerilog or VHDL).
• Experience with high-speed serial interfaces.
• Hardware verification practice.

Aufgaben

• Develop FPGA designs for modulator control and readout.
• Build host interfaces and drivers.
• Verify timing and throughput against the system budget.

Kenntnisse

Verilog/SystemVerilog

High-speed serial interfaces

Hardware verification

Jobbeschreibung

PHASER Hardware San Francisco, CA Full-time Mid-Senior

Write the gateware that programs PHASER's modulators and turns detector samples into results.

What you’ll do

• Develop FPGA designs for modulator control and readout
• Build host interfaces and drivers
• Verify timing and throughput against the system budget

What you’ll bring

• Experience with Verilog/SystemVerilog or VHDL
• High-speed serial interfaces
• Hardware verification practice

Nice to have

• Real-time signal processing

About TensaCo

TensaCo builds the compute and software that make AI faster, more efficient and accountable: PHASER, an optical approach to AI acceleration, and TensorCode, software for AI teams can check, correct and own.

TensaCo is an equal opportunity employer. We consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic.