FPGA Engineer for AI Accelerator: Modulator & Readout

TensaCo Inc; San Francisco (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

TensaCo Inc in San Francisco is looking for a mid-senior engineer to write gateware for PHASER modulators and translate detector samples into results. You will design FPGA logic and build interfaces with the rest of the system.

Responsibilities include verifying timing and throughput, working with Verilog/SystemVerilog or VHDL, and leveraging experience with high-speed serial interfaces and hardware verification.

Qualifications

• Experience with HDL languages (Verilog/SystemVerilog or VHDL).
• Experience with high-speed serial interfaces.
• Hardware verification practice.

Responsibilities

• Develop FPGA designs for modulator control and readout.
• Build host interfaces and drivers.
• Verify timing and throughput against the system budget.

Skills

Verilog/SystemVerilog

High-speed serial interfaces

Hardware verification

Job description

TensaCo Inc in San Francisco is looking for a mid-senior engineer to write gateware for PHASER modulators and translate detector samples into results. You will design FPGA logic and build interfaces with the rest of the system.

Responsibilities include verifying timing and throughput, working with Verilog/SystemVerilog or VHDL, and leveraging experience with high-speed serial interfaces and hardware verification.