FPGA Engineer

SoloPoint Solutions, Inc.; Fremont (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

SoloPoint Solutions, Inc. is seeking an experienced FPGA design engineer in Fremont, CA to develop high-speed timing generators and APG cores. The role involves Verilog-based implementation, rigorous timing constraints, and close collaboration with hardware and software teams.

The candidate will design and validate APG interfaces, memory blocks, and ECR modules, ensuring correct functionality from simulation to hardware bring-up, while maintaining documentation.

Qualifications

• Bachelor’s degree in electrical engineering.
• 5+ years of high-speed FPGA design experience.

Responsibilities

• Design the timing generators.
• The timing generators require fine timing control inside the FPGA.
• Design the signal formatting blocks inside the Test Controller FPGA.
• Design the Embedded Algorithmic Pattern Generator (APG) core.
• There will be multiple APG cores in the FPGA.
• Design the interface between the APGs and the Pin Electronics I/O.
• Implement the internal Vector Memory block.
• Implement the internal Error Capture RAM (ECR) block and the ECR data transfer block to move the data to the external memory.
• Ensure blocks are functional via simulation initially and then on the hardware when available.
• Work with the hardware design team and the software team to assist bring-up and driver development.
• Maintain and update relevant documentation and records as required.

Skills

FPGA timing control

Timing constraints

APG interface

Embedded pattern generator

Test bench/simulation

Education

Bachelor’s degree in electrical engineering

Tools

Verilog

APG core design

Job description

Qualifications:

• Bachelor’s degree in electrical engineering.
• 5 + years of large high speed FPGA design relevant experience.

Verilog Wafer-level semiconductor testing Design Experience using the internal PLL circuits (phase lock loops) Experience with design of Embedded Algorithmic Pattern Generator (APG) core & the interface between the APGs and the Pin Electronics I/O Good understanding of timing constraints in the FPGA to be able to achieve consistent timing results from build to build

Responsibilities:

• Design the timing generators.
• The timing generators require fine timing control inside the FPGA.
• Design the signal formatting blocks inside the Test Controller FPGA.
• Design the Embedded Algorithmic Pattern Generator (APG) core.
• There will be multiple APG cores in the FPGA
• Design the interface between the APGs and the Pin Electronics I/O
• Implement the internal Vector Memory block
• Implement the internal Error Capture RAM (ECR) block and the ECR data transfer block to move the data to the external memory
• Ensure blocks are functional via simulation initially and then on the hardware when available.
• Work with the hardware design team and the software team to assist bring-up and driver development.
• Maintain and update relevant documentation and records as required.