Sr. FPGA Design Engineer

SoloPoint Solutions, Inc.; Palo Alto (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

SoloPoint Solutions, Inc. in Palo Alto, CA seeks an experienced FPGA/RTL designer to develop and verify high-speed FPGA solutions on Xilinx Artix-7 platforms.

You will implement Verilog/SystemVerilog RTL and integrate PCIe IP to support real-time hardware operations. The ideal candidate has 10 years of hands-on FPGA experience, strong debugging skills, and a track record with high-speed interfaces such as PCIe, I2C, SPI, and CMIS.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering.
• 10 years of hands-on FPGA design, programming, and verification.
• Experience with Xilinx Vivado for Artix-7.
• Familiar with PCIe, I2C, SPI, and CMIS specs.
• Experience building digital testbenches to simulate chip behavior.
• Experience with self-checking testbenches and automated environments.
• Lab debugging with logic analyzers and FPGA tools.

Responsibilities

• Design RTL in Verilog/SystemVerilog for FPGA projects targeting Xilinx Artix-7.
• Integrate Xilinx PCIe Endpoint IP and develop custom CSR blocks to manage hardware operations over PCIe.
• Implement logic for high-frequency optical transceiver control and telemetry via CMIS over I2C.
• Perform hardware verification, system-level debugging, and timing closure to meet design specifications.

Skills

FPGA design

Verilog/SystemVerilog

Hardware verification

Testbenches

Lab debugging

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Xilinx Vivado (Artix-7)

PCIe IP

CMIS I2C SPI interfaces

I2C

SPI

CMIS

PCIe

Job description

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10 years of hands-on experience designing, programming, and verifying custom microchip logic (FPGAs).
• Experience with Xilinx software tools (Vivado) specifically tailored for the Artix-7 chip family
• Understanding ofof standard computer communication interfaces, including PCIe, I2C, SPI, and CMIS optical module specs
• Experiencebuilding digital test setups (testbenches) to simulate chip behavior and optimize code so signals run at maximum required speeds without errors
• Experiencewith verification using self-checking testbenches and automated test environments
• Lab debugging skills with logic analyzers, protocol analyzers, and FPGA debug tools

Responsibilities

• Design and implement RTL in Verilog/SystemVerilog for FPGA projects targeting Xilinx Artix-7
• Integrate Xilinx PCIe Endpoint IP and develop custom CSR blocks to manage hardware operations over PCIe
• Implement logic for high-frequency optical transceiver control and telemetry via CMIS over I2C
• Perform hardware verification, system-level debugging, and timing closure to meet design specifications