Senior Design Automation Engineer

Altera; United States; On-site; USD 149,000 - 216,000; Full time

Job summary

Altera in San Jose, California, seeks a Senior Design Automation Engineer to join the Design Methodology Automation and Infrastructure Team. You will architect and optimize automated FPGA design flows from RTL to GDSII, mentor junior engineers, and collaborate with cross‑functional teams to deliver scalable automation solutions for next‑generation products.

Requirements include a Bachelor's or Master's with 8+ years in IC design or design automation, strong Python/Tcl/C/C++, experience with EDA

Qualifications

• Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with 8+ years in IC Design or Design Automation.
• Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.
• Familiarity with ML/AI applications in EDA or design methodology optimisations.

Responsibilities

• Architect next‑generation unified FPGA/SoC design methodologies spanning Front‑End to Backend and DFt flows.
• Develop and integrate state‑of‑the‑art EDA solutions and automation tools for multiple design programs.
• Collaborate with leads to define new automation architectures and deploy them across product programs.
• Partner with EDA vendors to evaluate tool capabilities and drive design quality and throughput.
• Mentor junior engineers and drive cross‑functional initiatives to streamline FPGA design execution.

Skills

Python

Tcl

C/C++

Leadership

ML/AI in EDA

Education

Bachelor's or Master's in CS/EE

Tools

EDA tools

Job description

Job Details: Job Description:

About Altera At Altera™ our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology Automation and Infrastructure Team. The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera’s FPGA design flows—from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next‑generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross‑functional teams to deliver world‑class automation solutions.

Key Responsibilities

• Architect next‑generation unified FPGA/SoC design methodologies spanning Front‑End, handoff to Backend, Design Verification, Design‑For‑Test (DFT), Design Data Management/Release flows, and FPGA‑specific flows such as Design Intent and Configuration Management.
• Develop and integrate state‑of‑the‑art EDA solutions, including ML/AI‑enhanced tools, flows, and methodologies—sourced externally or developed internally—to create sustainable, scalable automation solutions for multiple chip design programs.
• Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.
• Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn‑around time, and enhance design optimization.
• Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.
• Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.
• Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.
• Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross‑functional initiatives to streamline FPGA design execution.
• Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.
• Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimisations.
• Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next‑generation capabilities.
• Mentor and provide technical leadership to junior engineers within the Design Automation organization.

Salary Range

We also offer incentive opportunities that reward employees based on individual and company performance. The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc.

$149,100 - $215,925 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorisations.

Minimum Qualifications

• Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 8+ years of experience in IC Design or Design Automation and experience in the following: Extensive experience with industry‑standard EDA tools and hands‑on expertise in design methodologies across multiple domains, such as Front‑End Logic Design flows, Design Intent and FPGA‑specific flows, Design Verification flows, and Design‑for‑Test (DFT) flows (with Back‑End flow knowledge considered a plus).
• Strong programming skills in Python, Tcl, C‑shell, C, C++, or similar languages.
• Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimisations.
• Proven leadership skills for driving collaborative, cross‑functional projects, with strong communication and influencing abilities.

Job Type

Regular
Shift: Shift 1 (United States of America)
Primary Location: San Jose, California, United States
Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy‑to‑use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end‑to‑end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.