FPGA Verification Engineer — Onsite El Segundo (Contract)

Inabia Software & Consulting Inc.; El Segundo (CA); On-site; USD 83,000 - 90,000; Full time

Job summary

Inabia Solutions & Consulting is seeking an experienced FPGA Design Verification Engineer to own verification activities from test planning through coverage closure and final signoff. You will develop verification environments, validate hardware and software interactions, and collaborate with architecture, design, and firmware teams to resolve issues.

This role requires 8–15 years of FPGA verification experience, strong SystemVerilog/UVM skills, and the ability to manage verification

Qualifications

• 8–15 years of FPGA design verification experience.
• Strong SystemVerilog/UVM testbenches and UVCs experience.
• Experience developing C-based tests and hardware/software verification flows.
• Bachelor's degree or equivalent in a related field.
• U.S. citizenship required.
• Onsite work in El Segundo, CA five days per week.
• DoD Secret clearance preferred.

Responsibilities

• Develop and maintain SystemVerilog/UVM testbenches and UVCs.
• Create verification plans for FPGA functionality and interfaces.
• Develop and integrate C-based tests and software build flows.
• Implement mailbox mechanisms to support hardware/software verification.
• Collect and analyze functional and code coverage, drive closure.
• Debug test failures and document defects with engineering teams.
• Collaborate with verification, architecture, design, and firmware teams.
• Improve verification environments to increase defect detection.
• Own verification deliverables and communicate risks.
• Mentor junior engineers and participate in technical reviews.

Skills

SystemVerilog/UVM

UVCs

C-based tests

FPGA design verification

Test planning

Coverage analysis

Debugging

Mentoring

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Job description

Inabia Solutions & Consulting is seeking an experienced FPGA Design Verification Engineer to own verification activities from test planning through coverage closure and final signoff. You will develop verification environments, validate hardware and software interactions, and collaborate with architecture, design, and firmware teams to resolve issues.

This role requires 8–15 years of FPGA verification experience, strong SystemVerilog/UVM skills, and the ability to manage verification