FPGA Design & Verification Engineer — High-Speed DSP & SOC

PDS Defense, Inc.

Town of Owego (NY)

On-site

USD 83,000 - 110,000

Full time

11 days ago

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Job summary

PDS Defense, Inc. in Owego, NY is seeking an FPGA Design/Verification Engineer to contribute to ASIC & FPGA development on an R&D program.

The role involves designing, testing, and integrating DSP, high-speed digital design, and SOC implementations on FPGA platforms, with experience in COTS control platforms and embedded processors on FPGA. You will work with Systems Architects and other engineers to create high-speed networking products, provide guidance to junior engineers, and contribute to

Qualifications

  • Experience with FPGA design tools (Xilinx Vivado, Intel Quartus, Synopsys Synplify).
  • Proficient in SystemVerilog.
  • Proficiency with HDL simulators, waveform viewers, and coverage tools.
  • Familiarity with hardware-in-the-loop (HIL) test setups and test equipment (e.g., JTAG, logic analyzers).
  • Experience with version control systems and configuration management.
  • Proficient in UVM.
  • Proficient in C.

Responsibilities

  • Design, test, and integrate DSP, high-speed digital design and SOCs on FPGA platforms.
  • Collaborate with Systems Architects and RF/Analog & Digital Circuit designers to deliver high-speed products.
  • Provide guidance and technical direction to junior engineers during design, verification, and test.

Skills

FPGA tools
SystemVerilog
HDL simulators
HIL test setups
Version control

Tools

Xilinx Vivado
Intel Quartus
Synopsys Synplify

Job description

PDS Defense, Inc. in Owego, NY is seeking an FPGA Design/Verification Engineer to contribute to ASIC & FPGA development on an R&D program.

The role involves designing, testing, and integrating DSP, high-speed digital design, and SOC implementations on FPGA platforms, with experience in COTS control platforms and embedded processors on FPGA. You will work with Systems Architects and other engineers to create high-speed networking products, provide guidance to junior engineers, and contribute to

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