FPGA Design Engineer - Onsite SF, Real-Time Lidar Systems

RiseMe; San Francisco (CA); On-site; USD 134,000 - 200,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Ouster in San Francisco, CA is seeking an FPGA Design Engineer to contribute to RTL development, verification and testing for our lidar systems. You will implement low-level logic and assist with system integration within the firmware team.

Required are a BS in Electrical/Computer Engineering, 2+ years FPGA experience, SystemVerilog/Verilog, C/C++, and toolchain experience with Vivado or Quartus. Onsite in SF with base pay in the range of $133,600–$200,000 and potential equity and benefits.

Qualifications

• BS in Electrical or Computer Engineering or equivalent required.
• 2+ years of FPGA development with HDL, simulation, and timing closure.
• Experience with SystemVerilog/Verilog and FPGA toolchains.

Responsibilities

• Develop RTL, verify and test FPGA code for next-gen lidar systems.
• Collaborate on system integration and design reviews with firmware team.
• Optimize real-time sensor performance and maintain HDL test benches.

Skills

SystemVerilog/Verilog

C/C++ programming

FPGA development

AXI bus interconnects

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent

Tools

Vivado

Quartus

Git

Job description

Ouster in San Francisco, CA is seeking an FPGA Design Engineer to contribute to RTL development, verification and testing for our lidar systems. You will implement low-level logic and assist with system integration within the firmware team.

Required are a BS in Electrical/Computer Engineering, 2+ years FPGA experience, SystemVerilog/Verilog, C/C++, and toolchain experience with Vivado or Quartus. Onsite in SF with base pay in the range of $133,600–$200,000 and potential equity and benefits.