United States
Remote
USD 80,000 - 120,000
Full time
30+ days ago
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Job summary
An established industry player is seeking a skilled FPGA Design Engineer to join their innovative team. In this role, you will be responsible for RTL block design and FPGA implementation using Xilinx Vivado, collaborating with a diverse group of engineers across hardware and software disciplines. You will create testbenches and ensure design verification while working with cutting-edge technology in a dynamic environment. This position offers the opportunity to contribute to exciting projects and advance your career in the field of FPGA design and verification. If you are passionate about electronics and eager to make an impact, this role is perfect for you.
Qualifications
- 5+ years of experience in IC or FPGA design.
- Strong understanding of Verilog/SystemVerilog and VHDL.
Responsibilities
- Design RTL blocks and implement FPGA systems using Xilinx tools.
- Create testbenches and verify designs for functionality.
Skills
RTL block design
SystemVerilog
Verilog
VHDL
FPGA implementation
Debugging
Collaboration with engineers
Education
Degree in Electrical/Electronic Engineering
Tools
FPGA Design Engineer
JOB RESPONSIBILITIES
- RTL block design (SystemVerilog / Verilog / VHDL)
- FPGA system assembly with in-house blocks, vendor macros and reference-designs.
- Testbench creation and design verification
- FPGA implementation in Xilinx Vivado tool-set, with complete timing constraints.
- Setup and debug with Xilinx ILA
- Potential collaboration with hardware, software, analog/digital IC design engineers.
REQUIREMENTS
- Degree in Electrical/Electronic Engineering or similar technical field.
- Minimum of 5 years of experience in IC or FPGA design, with 5-10 years in industry.
- Able to understand both Verilog/SystemVerilog and VHDL
PREFERENCES
- Experience with Xilinx Ultrascale+ devices
- Experience working with DDR RAM controllers and efficient memory access
- Prior experience with high-speed interfaces (DPHY, LVDS, GbE) on FPGA a significant advantage.