Hardware Design Engineer 5

HireTalent; Fort Collins (CO); Remote; USD 100,000 - 140,000; Full time

Job summary

An established industry player is seeking a Hardware Design Engineer to join a dynamic team focused on cutting-edge FPGA design verification. This fully remote position offers the chance to work on impactful projects like Azure Boost, where you'll develop and execute comprehensive verification plans using UVM and System Verilog. Enjoy a flexible workstyle with strong autonomy, allowing you to focus on coding and debugging in a collaborative environment. If you're passionate about hardware engineering and looking for a role that emphasizes creativity and innovation, this opportunity is perfect for you.

Qualifications

• 10+ years of experience in hardware design and verification.
• Proficiency in UVM and System Verilog is essential.

Responsibilities

• Develop and execute verification test plans for complex IPs.
• Analyze project information for planning and execution.
• Build and modify prototypes using computer simulation.

Skills

UVM Testbench Development

System Verilog

Debugging Skills

Verilog RTL Programming

Analytical Skills

Problem Solving

Creativity

Education

Bachelor's degree in Engineering

Job description

Job Title: Hardware Design Engineer 5
Job Location: Fully Remote
Job Duration: 1 Month On W2 (High Chances of Extention)

Summary:
Be part of a team working on design verification for complex IPs and sub-systems that are a part of modern FPGAs. Develop and execute verification test plans for IPs and/or sub-systems. This includes: development of testbench infrastructure, testcase creation, implementing checkers, writing functional coverage and assertions, develop common/reusable verification components for reuse across teams, perform coverage analysis and closure, run simulations and regressions, triage and debug test failures. Ideal candidate has extensive experience of IP level verification using UVM and System Verilog within the last 3 years. Knowledge of AMBA AXI protocol is preferred, but not required.

Job Responsibilities:
• Analyze information for project planning and execution.
• Create and modify existing environments and components to verify features in a UVM simulation environment.
• Build, test, and modify product prototypes using working models or theoretical models constructed with computer simulation.
• Evaluate factors such as reporting formats required, constraints, and need for security restrictions to determine hardware configuration.
• Monitor functioning of equipment and make necessary modifications to ensure system operates in conformance with specifications.

Skills:
• Creativity, verbal and written communication skills, analytical and problem solving ability.
• Team player and detail oriented.
• Basic knowledge of Verilog RTL programming language.
• Advanced knowledge of UVM and System Verilog programming languages.
• Basic knowledge of the practical application of engineering science and technology.
• Basic knowledge of ASIC or FPGA based verification.
• Previous experience with design related to hardware engineering field.

Education/Experience:
• Bachelor's degree in engineering required.
• 10+ years experience required.

Typical Day in the Role:
• Purpose of the Team: The purpose of this team is to work in Azure Core on the storage and networking team. They are developing an FPGA to accelerate the storage and networking flow.
• Key projects: This role will contribute to a project externally known as "Azure Boost." This project involves contributing to the cloud by developing an FPGA to accelerate storage and networking flow.
• Typical task breakdown and operating rhythm: The role will consist of 5% of meeting, mostly for coordination with the lead engineer; 60% of coding, specifically in System Verilog and UVM test benches, and 35% of debugging and testing, including handling regression failures.

Compelling Story & Candidate Value Proposition:
• What makes this role interesting? - This role provides the opportunity to be engaged in hands-on coding, and impactful project such as Azure Boost
• Unique Selling Points: This role is being offered as a remote position which provides a flexible workstyle. There is strong autonomy on the team - the freedom to work independently while being guided by engineering, allowing for a flexible and self-directed work environment. Lastly, there is minimal overhead: The team is small, which means there is less overhead and more focus on actual development and debugging tasks.

Requirements:
• Years of Experience Required: 10+ overall years of experience in the field.
• Degrees or certifications required: BA in Engineering is required to be eligible for this role.
• Disqualifiers: candidate lacking experience in System Verilog or UVM, particularly in creating and writing test benches will not be eligible for the role.
• Best vs. Average: The ideal resume would contain proficiency in UVM testbench development and maintenance, strong knowledge of System Verilog, and excellent debugging skills for tests using waves and logs..
• Performance Indicators: Performance will be assessed based on Task Delivery: Completing assigned tasks and meeting deadlines as per the schedule, Code Contributions: Regularly committing and landing code through pull requests, and Overall Schedule Adherence: Maintaining the project schedule and meeting deadlines.

Top 3 Hard Skills Required + Years of Experience:
• Recent years experience with UVM Testbench Development and Maintenance: Experience in creating and maintaining UVM testbenches..
• Recent years experience with Strong Knowledge of System Verilog: Proficiency in coding with System Verilog..
• Recent years experience with Debugging Skills: Ability to debug tests using waves and logs.

About the company

HireTalent is an executive search firm and temporary staffing solutions provider that specializes in providing direct-hire, contract-to-hire, MSP staffing, Vendor Neutral Program staffing, and consulting services to clients at a national level.