FPGA Design Automation & Methodology Engineer

Socket.dev; San Jose (CA); On-site; USD 133,000 - 158,000; Full time

Job summary

Altera is seeking a Design Automation Engineer to join the Design Infrastructure and Automation Team in San Jose, CA. You will build and maintain core automation infrastructure for RTL to bitstream, delivering scalable, reliable design flows and accelerating development cycles for FPGA products.

You will collaborate with RTL designers, physical design, and verification teams, applying AI to boost productivity, while evaluating new EDA vendors and integrating CI/CD and cloud-based orchestration

Qualifications

• 4+ years of experience with EDA tools and FPGA/ASIC design flows (e.g., lint, cdc).
• 4+ years of experience in Unix/Linux environments and scripting/programming languages such as Python, Perl, and Shell.

Responsibilities

• Develop and maintain in-house tools and infrastructure for end-to-end design flow automation.
• Apply and develop AI solutions that enhance productivity and efficiency for chip design.
• Collaborate cross-functionally with RTL designers, physical design engineers, verification teams, and tool vendors to deliver scalable solutions.
• Evaluate and implement new EDA vendor technologies and frameworks to enhance design development process.
• Drive process improvements, standardization, and reusable components across automation infrastructure.

Skills

Python

Shell scripting

Unix/Linux

Git

Cross-functional collaboration

Education

Bachelor's or Master's degree in CS / EE / related field

Tools

EDA tools

CI/CD

Cloud-based orchestration

Job description

Altera is seeking a Design Automation Engineer to join the Design Infrastructure and Automation Team in San Jose, CA. You will build and maintain core automation infrastructure for RTL to bitstream, delivering scalable, reliable design flows and accelerating development cycles for FPGA products.

You will collaborate with RTL designers, physical design, and verification teams, applying AI to boost productivity, while evaluating new EDA vendors and integrating CI/CD and cloud-based orchestration