FPGA Design Architect: High-Speed Protocols & Validation

Synopsys Inc; Sunnyvale (CA); On-site; USD 140,000 - 180,000; Full time

Benefits offered by this job

Comprehensive health benefits

Wellness programs

Financial benefits

Job summary

Synopsys Inc in Sunnyvale is looking for an expert to develop Speed Adapter solutions that bridge high-speed I/O interfaces and facilitate system-level validation of silicon designs. You will work closely with teams across hardware and software to ensure customer deliverables meet stringent specifications, enhancing the adoption of emerging protocols such as PCIe Gen7 and CXL 4.0.

Your deep expertise in RTL design and debugging, combined with your ability to influence architectural decisions, will have a significant impact on the next generation of high-performance chips.

Qualifications

• 12+ years of relevant experience.
• Deep hands-on experience with UCIe, PCIe (Gen4 or later), or CXL (2.0 or later).
• Experience with system-level validation across hardware/software.

Responsibilities

• Design and develop Speed Adapter solutions for PCIe Gen5/Gen6 and other protocols.
• Implement protocol logic on FPGA-based platforms.
• Collaborate with IP and emulation teams for integrated solutions.

Skills

RTL development skills

High-speed I/O protocols

Debugging skills

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

ZeBu

HAPS

Job description

Synopsys Inc in Sunnyvale is looking for an expert to develop Speed Adapter solutions that bridge high-speed I/O interfaces and facilitate system-level validation of silicon designs. You will work closely with teams across hardware and software to ensure customer deliverables meet stringent specifications, enhancing the adoption of emerging protocols such as PCIe Gen7 and CXL 4.0.

Your deep expertise in RTL design and debugging, combined with your ability to influence architectural decisions, will have a significant impact on the next generation of high-performance chips.