Foundry Technology Enablement Engineer (PPA, DTCO)

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a technically driven professional to lead technology and design enablement for advanced silicon technology in San Jose, CA. You will work with design, architecture, technology and product engineering teams to ensure power, performance, and area targets are met, while enabling PDks, IP, and verification collateral for production readiness.

The ideal candidate has a strong foundation in semiconductor technology and industry-standard IC design/verification flows, with 8+ years of

Responsibilities

• Collaborate with internal design, architecture, technology and product teams to align foundry process with product performance, power, and area (PPA) targets.
• Drive technology development and product evaluation by ensuring the appropriate readiness of process design kits (PDKs) and design/verification flows.
• Serve as a technical liaison with internal and external teams to support process technology and product definitions, testchip and product designs, design-for-manufacturing (DFM) practice definition, and silicon analysis and debug.
• Support technology-to-product issue resolution from early technology evaluation to NPI phases, proposing data-driven solutions for device, interconnect, or yield challenges.
• Coordinate with reliability and packaging teams to evaluate and mitigate product reliability and Si-package interaction risks.

Job description

AMD is seeking a technically driven professional to lead technology and design enablement for advanced silicon technology in San Jose, CA. You will work with design, architecture, technology and product engineering teams to ensure power, performance, and area targets are met, while enabling PDks, IP, and verification collateral for production readiness.

The ideal candidate has a strong foundation in semiconductor technology and industry-standard IC design/verification flows, with 8+ years of