Principal Engineer-TD Foundry Engineering

Intel; Hillsboro (OR); On-site; USD 140,000 - 210,000; Full time

Job summary

Intel seeks a Principal Engineer to lead the foundry strategy within the LTD organization, guiding customers through design tape-out to pre-silicon evaluation and into HVM. You will shape roadmaps for yield, performance, and process integration across device types, while driving NPI execution and design enablement initiatives.

The role requires executive leadership, cross-functional collaboration, and deep semiconductor knowledge to accelerate time-to-market for flagship products in the AI era.

Responsibilities

• Strategic Yield / Performance Governance: Establish the overarching yield strategy and governance framework for the foundry product lifecycle, ensuring a seamless transition from design to HVM.
• Roadmap Architecture: Define and steer the long-term yield / performance goals, technology features and roadmaps for foundry customer silicon in alignment with Intel Business Group, Technology Development, Design Technology Platform.
• Systemic Loss Mitigation: Lead high-level strategic initiatives to identify and eliminate systematic and parametric yield detractors, directing cross-functional teams across Process Integration, Device Engineering, and Defect Metrology.
• Predictive Modeling Strategy: Oversee the development of advanced predictive models, using AI/ML, for parametric and defective loss, ensuring projection accuracy for test chips and high-volume products.
• Metric Correlation Frameworks: Define the standards for correlating inline process metrics with end-of-line yield and performance to institutionalize better process control across the organization.
• NPI Strategic Leadership: Direct the execution of New Product Introduction (NPI), overseeing wafer lot progress, skew split strategy, and targeting for flagship customer products.
• Device Performance Strategy: Lead the analysis of device performance and variability for logic, SRAM, and emerging device types to ensure industry-leading specifications.
• Experimental Design Oversight: Architect complex Design of Experiments (DOE) and skew split plans to optimize product health and accelerate time-to-market.
• Technology Compliance: Ensure organizational adherence to critical customer technology metrics, including fab process yield, E-Test (ET), WAT/C, and Cp/Cpk.
• PDK Strategic Vision: Drive the vision for high-quality Process Design Kits (PDKs), ensuring they are optimized for customer success through rigorous validation of metrology and yield data.
• Simulation Standards: Oversee the Sil2Sim (Silicon-to-Simulation) correlation frameworks and layout effect assessments to reduce design iterations.
• Governance and Risk Management: Chair or provide executive guidance to the Waiver Review Board (WRB) to assess and mitigate risks associated with DRC violations.
• IP Ecosystem Development: Lead the strategy for intellectual property (IP) design activities, ensuring robust design rules and seamless mask tape-out execution.

Job description

Job Details:

Job Description:

As the world's largest chip manufacturer, and a global leader in innovation and new technology, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.

What we offer:

We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.

What we do:

Join the Logic Technology Development (LTD) organization, a powerhouse of process technology innovation driving Intel's IDM 2.0 strategy to exceed the aspirations of our global customers. We are seeking a visionary Principal Engineer to lead the charge in Intel's foundry revolution, serving as a strategic technical architect and executive partner in guiding our most critical customers through the entire product development lifecycle. In this leadership capacity, you will orchestrate multidisciplinary strategies spanning device engineering, product integration, and yield analysis to steer customers from critical design tape-out and pre-silicon evaluation through to NPI silicon qualification. Furthermore, you will define the strategic roadmap for Far Back End (FBE) expertise in test, bump, and assembly, ensuring a seamless, scalable transition into High Volume Manufacturing (HVM) and volume ramp. This high-impact role provides executive technical leadership, engages directly with customers, drives the success of multi-billion-dollar programs, and helps shape the future of the global semiconductor industry in the AI innovation era.

What you will do:

We are seeking an elite level of semiconductor expertise to drive the strategic direction of foundry technology development. Based on your leadership experience, your focus will include:

Yield Engineering and Performance Optimization

• Strategic Yield / Performance Governance: Establish the overarching yield strategy and governance framework for the foundry product lifecycle, ensuring a seamless transition from design to HVM.
• Roadmap Architecture: Define and steer the long-term yield / performance goals, technology features and roadmaps for foundry customer silicon in alignment with Intel Business Group, Technology Development, Design Technology Platform.
• Systemic Loss Mitigation: Lead high-level strategic initiatives to identify and eliminate systematic and parametric yield detractors, directing cross-functional teams across Process Integration, Device Engineering, and Defect Metrology.
• Predictive Modeling Strategy: Oversee the development of advanced predictive models, using AI/ML, for parametric and defective loss, ensuring projection accuracy for test chips and high-volume products.
• Metric Correlation Frameworks: Define the standards for correlating inline process metrics with end-of-line yield and performance to institutionalize better process control across the organization.

Product Integration and NPI Execution

• NPI Strategic Leadership: Direct the execution of New Product Introduction (NPI), overseeing wafer lot progress, skew split strategy, and targeting for flagship customer products.
• Device Performance Strategy: Lead the analysis of device performance and variability for logic, SRAM, and emerging device types to ensure industry-leading specifications.
• Experimental Design Oversight: Architect complex Design of Experiments (DOE) and skew split plans to optimize product health and accelerate time-to-market.
• Technology Compliance: Ensure organizational adherence to critical customer technology metrics, including fab process yield, E-Test (ET), WAT/C, and Cp/Cpk.

Design Enablement and PDK Management

• PDK Strategic Vision: Drive the vision for high-quality Process Design Kits (PDKs), ensuring they are optimized for customer success through rigorous validation of metrology and yield data.
• Simulation Standards: Oversee the Sil2Sim (Silicon-to-Simulation) correlation frameworks and layout effect assessments to reduce design iterations.
• Governance and Risk Management: Chair or provide executive guidance to the Waiver Review Board (WRB) to assess and mitigate risks associated with DRC violations.
• IP Ecosystem Development: Lead the strategy for intellectual property (IP) design activities, ensuring robust design rules and seamless mask tape-out execution.