Formal Verification Engineer - Equity Eligible

NVIDIA Corporation; Santa Clara (CA); Presencial; USD 100.000 - 190.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Equity

Benefits

Descripción de la vacante

NVIDIA Corporation in Santa Clara, CA is seeking a Formal Verification Engineer to join our formal verification team for the industry’s leading chips. The role focuses on owning the formal verification of RTL units for next generation chip designs, leveraging deep architectural and micro-architectural knowledge and effective verification methodologies.

The candidate will develop FV test plans, verification environments, and proofs, and collaborate with design and verification teams to ensure

Formación

• BS or MS in CS/CE/EE/Mathematics or equivalent experience.
• Strong analytical skills to solve difficult problems.
• Knowledge/Experience in formal verification techniques.
• Strong knowledge of architectures of CPU/GPU designs and digital logic.
• Understanding of abstraction techniques for effective verification.
• Hands-on experience with HDLs such as Verilog / System Verilog.
• Ability to understand RTL quickly.
• Understanding of temporal logic assertions.
• Preferable experience with Formal Verification Tools (eg. Jasper, IFV, SMV, SPIN)
• Excellent communication skills with ability to work with team members and collaborate effectively.

Responsabilidades

• Developing comprehensive FV testplan documents.
• Identifying key behaviors for verification of DUT and creating a verification plan.
• Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
• Applying various FV techniques to proof correctness of digital designs.
• Debugging RTL to identify failure scenarios.
• Developing scripts to automate the verification process.
• Review formal setups and proofs with design and verification teams.

Conocimientos

Formal verification

Computer architecture

Analytical skills

Educación

BS or MS in CS/CE/EE/Mathematics

Herramientas

Verilog/SystemVerilog

Jasper

IFV

SMV

SPIN

Descripción del empleo

NVIDIA Corporation in Santa Clara, CA is seeking a Formal Verification Engineer to join our formal verification team for the industry’s leading chips. The role focuses on owning the formal verification of RTL units for next generation chip designs, leveraging deep architectural and micro-architectural knowledge and effective verification methodologies.

The candidate will develop FV test plans, verification environments, and proofs, and collaborate with design and verification teams to ensure