Formal Verification Engineer

ChipAgents; San Jose (CA); On-site; USD 150,000 - 350,000; Full time

Benefits offered by this job

Unlimited PTO

Full benefits (medical, vision, dental, 401k)

Free lunch, drinks, and snacks

Job summary

ChipAgents is seeking a Formal Verification Engineer to work with AI engineering and EDA teams. The role focuses on formal methods and assertion-based verification in semiconductor design. Candidates should have strong expertise in formal verification methodologies and experience with tools like JasperGold and SystemVerilog Assertions.

This position offers a competitive salary ranging from $150K to $350K per year, plus equity and full benefits including unlimited PTO. Join us to shape the future of semiconductor design.

Qualifications

• Strong expertise in formal verification methodologies and signoff flows.
• Deep knowledge of SystemVerilog Assertions and assertion-based verification.
• Proficiency in Python or scripting for verification automation.

Responsibilities

• Collaborate on formal verification workflows.
• Develop and debug SystemVerilog Assertions and properties.
• Use verification tools to analyze RTL designs and prove correctness.
• Create formal verification examples to train AI agents.
• Support evaluation of AI-assisted verification productivity.

Skills

Formal verification methodologies

Experience with JasperGold

SystemVerilog Assertions

Debugging counterexamples

Python scripting

Tools

JasperGold

VC Formal

Questa Formal

Job description

About ChipAgents

ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups. Our platform accelerates RTL development, functional verification, and simulation—unlocking new levels of productivity and design quality.

Role Overview

We are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA teams to build advanced agentic AI systems for semiconductor verification.

Your expertise in formal methods, property specification, assertion-based verification, and proof debugging will help shape how AI systems reason about complex hardware behavior. You will play a central role in teaching our AI agents how verification engineers develop properties, analyze counterexamples, close proof convergence gaps, and validate RTL designs with mathematical rigor.

This is a unique opportunity to apply deep formal verification expertise at the frontier of AI-assisted chip design.

Key Responsibilities

• Collaborate with AI engineers and researchers to model and codify formal verification workflows.

• Develop, refine, and debug SystemVerilog Assertions, formal properties, assumptions, constraints, and coverage objectives.

• Use formal verification tools to analyze RTL designs, prove design correctness, and identify functional bugs.

• Create reusable formal verification examples, design patterns, proof strategies, and edge cases to train and evaluate AI agents.

• Help AI systems interpret design specifications, generate properties, reason about RTL behavior, and debug counterexamples.

• Support benchmarking and evaluation of AI-assisted formal verification productivity across realistic IP and SoC verification tasks.

• Work closely with customers, product, and research teams to translate formal verification pain points into automated AI workflows.

• Contribute to methodology development for assertion-based verification, formal apps, equivalence checking, connectivity checking, and coverage closure.

Qualifications

• Strong expertise in formal verification methodologies and signoff flows.

• Hands-on experience with JasperGold, VC Formal, Questa Formal, or equivalent tools.

• Deep knowledge of SystemVerilog Assertions (SVA) and assertion-based verification.

• Experience proving complex properties, debugging counterexamples, and achieving formal closure.

• Familiarity with SAT/SMT-based reasoning and formal verification fundamentals.

• Experience with CDC, RDC, lint, and static verification methodologies.

• Strong RTL design and microarchitecture understanding.

• Experience verifying production IPs, subsystems, or SoCs.

• Proficiency in Python, Tcl, or scripting for verification automation.

• Interest in applying AI/LLMs to hardware design and verification workflows

Why ChipAgents

• Work at the frontier of AI and semiconductor design.

• Collaborate with a world-class team spanning AI, systems, and EDA.

• Shape a foundational shift in how chips are built.

What we offer

• $150K/yr – $350K/yr + Offers Equity. We are open to discuss above-scale compensation with exceptional candidates on a case-by-case basis.

• Unlimited PTO and full benefits (medical, vision, dental, 401k).

• Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.