Field-Programmable Gate Arrays Engineer

OKAYA INFOCOM; Melbourne (FL); On-site; USD 90,000 - 120,000; Full time

Job summary

OKAYA INFOCOM is seeking an FPGA/Hardware Engineer (DO-254) in Melbourne, FL, onsite. The role requires expert verification with SystemVerilog/UVM or equivalent lab/design verification experience. Strong Xilinx experience is a plus and interaction with India GETC‑I site is expected.

Responsibilities include RTL design and simulation, UVM environments, DO-254 artifacts, and DO-254 compliance for AEH DAL-A certification. 5+ years hardware experience preferred.

Qualifications

• Expert-level verification engineer with SystemVerilog/UVM experience or lab testing/design verification background.
• FPGA verification in lab testing or hardware verification testing.
• Experience with Xilinx devices is a strong plus.

Responsibilities

• Develop RTL code and testbenches using VHDL/Verilog/SystemVerilog.
• Create UVM environments and perform timing, linting, and CDC analyses.
• Prepare DO-254 artifacts for AEH DAL-A certification and assist FAA SOI audits.
• Capture requirements and drive architecture, synthesis, and place-and-route.

Skills

SystemVerilog

UVM

FPGA verification

Xilinx

lab testing

communication

Education

STEM degree

Tools

VHDL

Verilog

SystemVerilog

Job description

Job Title: FPGA/Hardware Engineer/ Electrical Engineer (DO-254)

Location :- Melbourne, FL(Onsite)

Job Description & Skill Requirement:

Expert‑level verification engineer with strong SystemVerilog and UVM experience. As an alternative to SystemVerilog/UVM, we are open to candidates with a verification background in lab testing and/or design verification testing. Experience with design on Xilinx products would be a strong plus.

Required Skills:

• Expert‑level verification engineer with strong SystemVerilog and/ or UVM experience or
• FPGA verification in lab testing and/or Hardware FPGA design verification testing
• Experience with design on Xilinx products would be a strong plus
• expected to communicate effectively with emerging engineers at the India GETC‑I site and provide both technical and process (DO-254) guidance to the verification team.

Core Responsibilities

• RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
• Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
• DO-254 Certification: Create artifacts required for Airborne Electronic Hardware (AEH) DAL-A certification and participate in FAA SOI audits.
• Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. [1]

Key Qualifications

• Experience: Substantial hands‑on FPGA or ASIC development experience (typically 5+ years for a senior designation).
• Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.
• Avionics Knowledge: Familiarity with design assurance standards (DO-254) is highly preferred.