FE Engineer

Apple, Inc.; Cupertino (CA); On-site; USD 150,000 - 225,000; Full time

Benefits offered by this job

Discretionary bonuses or commissions

Relocation assistance

Stock programs

Job summary

APPLE INC in Cupertino, California, is seeking a highly skilled CPU micro-architect and RTL engineer to drive architecture, timing, and power efficiency across high-performance cores. You will refine RTL, collaborate with verification and physical design teams, and push innovations that balance speed with energy use.

The role requires a Master’s in Computer Engineering, deep CPU and VLSI knowledge, and proficiency in C++, Python, and Perl.

Qualifications

• Master's degree in Computer Engineering or related field.
• Experience with RTL design using Verilog to meet power, performance, and area targets.
• Strong knowledge of advanced computer architecture for CPUs.
• Knowledge of VLSI to optimize frequency, power, and area.
• Experience with out-of-order superscalar processor techniques.
• Understanding of branch prediction techniques to improve CPU performance.
• Familiarity with cache hierarchies and CPU performance optimization.
• Proficiency in C++, Python, and Perl for performance/power modeling.
• Ability to evaluate power-performance curves and power trade-offs.

Responsibilities

• Perform micro-architecture development and specification from exploration to detailed specs.
• Develop RTL design refinements targeting power, performance, and area goals.
• Collaborate with performance verification to ensure RTL meets targets.
• Work with cross-functional teams to implement and verify physical design and timing closure.
• Investigate power-hungry blocks and apply micro-architectural changes with minimal performance impact.
• Support design verification, test benches, and formal methods.

Skills

Verilog RTL

Computer architecture

VLSI

Out-of-order CPU

Branch prediction

Cache hierarchies

Programming: C++, Python, Perl

Power-performance trade-offs

Education

Master's degree in Computer Engineering

Job description

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Perform micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research, and arriving at a detailed specification. Develop, assess, and refine of RTL design to target power, performance, area and timing goals. Explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance. Work with multi-functional engineering teams to implement and verify physical design on the aspects of timing, area, reliability, testability, and power. Leverage understanding of out-of-order processor architecture and micro-architecture, Low level microarchitecture techniques, and the tradeoff between power and performance. Implement CPU design modules that meet the performance and power goals. Leverage debugging skills and understanding of C/C++ and perl to provide support for the scripts and for the feature exploration process. Support the verification team in test bench development, formal methods, and simulation/emulation for formal verification. Work with the Design verification team to make required modifications, ensuring that these designs are functionally correct. Work on performance exploration features - thinking about new micro-architectural features and working with architects to ensure the feasibility of the design by implementing raw RTL changes that are required for the design feature. Search for the power-hungry blocks to reduce the power consumption of these hardware modules using micro-architectural changes that have minimal impact on performance. Work with the Physical Design team to reduce the timing pressure on the design to make the feature meet the timing goals and for timing closure. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Computer Engineering or related field
• Experience and/or education must include:
• Utilizing Verilog expertise to create high-quality functional RTL that meets power, performance, and area requirements.
• Leveraging advanced computer architecture knowledge to design state-of-the-art CPUs.
• Applying VLSI knowledge to efficiently enhance the frequency, power, and area of a CPU.
• Employing out-of-order superscalar processor techniques to design a CPU.
• Applying advanced branch prediction techniques to improve CPU branch predictors, thereby increasing efficiency and performance in modern CPUs.
• Utilizing knowledge of cache hierarchies to enhance cache performance in the CPU.
• Applying modeling skills in C++, Python, and Perl to conceptualize new performance and power concepts, thereby improving CPU performance and efficiency.
• Applying knowledge of power-performance curves to assess and improve power-performance curves by researching innovative low-power and high-performance architectures and techniques.
• Applying CPU architecture knowledge to develop power models that help evaluate power trade-offs for next-generation CPUs.
• Utilizing knowledge of various CPU workloads and characteristics, such as code footprint, data footprint, and usage, to evaluate detailed power, performance, and area trade-offs and build a CPU tailored for the target consumers.

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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