ESD & Latch-Up Reliability Engineer - Tech Development

Intel; Hillsboro (OR); On-site; USD 156,000 - 220,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health & retirement benefits

Job summary

Intel in Hillsboro, Oregon is seeking an Experienced Hire engineer to advance ESD and latch-up reliability in circuits. You will design test structures, run experiments, and perform TLP characterization to inform design rules for internal and foundry teams.

The role emphasizes collaborating with analog circuit designers and planning test layouts for chips, with an emphasis on data-driven reliability analysis and published findings.

Qualifications

• Master's degree in Electrical Engineering, Reliability Engineering, Physics, or related technical field.
• 3+ years experience in ESD or LU reliability engineering.
• 3+ years of experience with device physics, device characterization and/or basic VLSI design knowledge.

Responsibilities

• Develop solutions and design rules to ensure ESD and latch-up reliability in circuits.
• Design test structures and run experiments during technology development.
• ESD characterization on test structures using transmission line pulse (TLP).
• Develop, document, and publish design rules to aid internal and foundry design teams.
• Serve as a consultant to design teams to address ESD risks in analog circuits.

Skills

Reliability engineering

Test structure design

Data analysis

TLP measurement

Education

Master's degree

PhD preferred

Tools

TLP measurement

JMP

Excel

Job description

Intel in Hillsboro, Oregon is seeking an Experienced Hire engineer to advance ESD and latch-up reliability in circuits. You will design test structures, run experiments, and perform TLP characterization to inform design rules for internal and foundry teams.

The role emphasizes collaborating with analog circuit designers and planning test layouts for chips, with an emphasis on data-driven reliability analysis and published findings.