End-to-End SoC Co-Design Tech Lead

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 232,000 - 368,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation seeks a Chip Lead in its Silicon Co-Design Group to serve as the technical lead for a major silicon program, ensuring end-to-end technical integrity and cross-functional cohesion across design, validation, software, and manufacturing.

This role requires deep expertise in post-silicon bring-up and a track record of guiding technical decisions across functions without direct reporting authority, with strong emphasis on reliability and scalable methodology.

Qualifications

• BS or MS in Electrical or Computer Engineering with 15+ years in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company.
• Proven track record in end-to-end SoC/ASIC architecture with impact on specific subsystems such as HBM, SerDes, power/thermal, or packaging.

Responsibilities

• Serve as the single technical point of contact for multi-functional decisions and trade-offs.
• Co-lead program-level feature integration from chip to system and surface interdependencies.
• Resolve multi-functional bugs by translating symptoms into root-cause closures (HBM, power/thermal, high-speed I/O, packaging).
• Steward the qualification playbook and capture reusable methodologies across SCG programs.
• Shape the program's technical narrative for executive leadership with risk and mitigation options.
• Mentor Chip Leads on adjacent silicon programs and contribute to SCG-wide methodology.
• Lead Critical Debug and SCG Technical Execution forums and represent the chip externally with early risk insight.

Skills

Post-silicon bring-up leadership

Cross-functional leadership

Silicon validation

Education

BS/MS in Electrical or Computer Engineering

Job description

NVIDIA Corporation seeks a Chip Lead in its Silicon Co-Design Group to serve as the technical lead for a major silicon program, ensuring end-to-end technical integrity and cross-functional cohesion across design, validation, software, and manufacturing.

This role requires deep expertise in post-silicon bring-up and a track record of guiding technical decisions across functions without direct reporting authority, with strong emphasis on reliability and scalable methodology.