Embedded CPU Performance Architect, Platform Design

Apple Inc.; Beaverton (OR); Hybrid; USD 170,000 - 270,000; Full time

Job summary

Apple Inc. is seeking an Embedded CPU Performance Architect to drive efficiency and performance for embedded CPUs powering iPhone, iPad, Mac and more. You will explore architectural features, collaborate with micro-architects, and refine ideas for implementability while ensuring RTL aligns with performance simulations.

The role focuses on modeling, data-driven decisions, and cross-team collaboration to squeeze every drop of performance per milliwatt in a broader CPU platform architecture context.

Qualifications

• Experience in CPU and SOC architecture and micro-architecture.
• Experience with performance simulation environments.
• Object-oriented programming skills in C/C++
• Experience in a scripting language such as Perl or Python
• MS or PhD in Electrical or Computer Engineering or Computer Science
• Understanding of common data structures and algorithms
• Familiarity with SIMD, vector, or accelerator architectures

Responsibilities

• Define CPUs for embedded applications across Apple products, balancing performance, power and area.
• Model solutions to optimize performance per watt and throughput.
• Collaborate with CPU designers to assess feasibility through modeling and RTL correlation.
• Correlate RTL with CPU performance simulators to ensure targets are met.
• Analyze workloads to identify bottlenecks and opportunities for improvement

Skills

CPU architecture

SOC architecture

micro-architecture

C/C++ programming

Python

Perl

Education

MS or PhD in Electrical/Computer Engineering or Computer Science

Job description

Apple Inc. is seeking an Embedded CPU Performance Architect to drive efficiency and performance for embedded CPUs powering iPhone, iPad, Mac and more. You will explore architectural features, collaborate with micro-architects, and refine ideas for implementability while ensuring RTL aligns with performance simulations.

The role focuses on modeling, data-driven decisions, and cross-team collaboration to squeeze every drop of performance per milliwatt in a broader CPU platform architecture context.